TLK2226_09 Datasheet, PDF (21/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
www.ti.com
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
Clock Recovery
A baud rate clock is extracted from the 10-bit encoded serial data stream independently on each channel. After
powering up the device, it takes approximately 8 µs before data is received and the device is ready to transmit.
The receive clock locks to the input within 2 µs after a valid input data stream is applied. The received data is
de-serialized and byte aligned to IEEE802.3z /K28.5-characters (while in 1.25Gbps mode). In the absence of
input data, the clock recovery circuit will lock onto the reference clock frequency REFCLK; once valid data is
again presented at the serial inputs, a time will elapse before the channel reacquires lock and performs data and
clock recovery functions.
Deserializer
For each channel, serial data is received on the RXx+/RXx– pins. The interpolator and clock recovery circuit will
lock to the data stream if the clock to be recovered is within ±200 PPM of the internally generated bit rate clock,
assuming a ±100 PPM tolerance on the reference clock. The recovered clock is used to retime the input data
stream. The serial data is then clocked into the serial-to-parallel shift registers. If enabled, the 10-bit wide
parallel data is then fed into 8b/10b decoders. The parallel data for each channel is fed into a FIFO buffer where
the output is synchronized to REFCLK when CTC is on. In case CTC is off data is synchronized to 1/10^th of the
received bit clock.
Byte Alignment Logic (1.25 Gbps mode)
Under default conditions, the TLK2226 uses the IEEE802.3z defined 10-bit K28.5 character (comma character,
positive disparity) word alignment scheme . The following sections explain how this scheme works and how it
realigns itself. When parallel data is clocked into a parallel to serial converter, the byte boundary that was
associated with the parallel data is lost in the serialization of the data. When the serial data is received and
converted to parallel format again, a method is needed to be able to recognize the byte boundary again.
Generally, this is accomplished through use of a synchronization pattern. This is a unique a pattern of 1’s and
0’s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B
encoding makes allowance for a special pattern called the comma (B’0011111’) which is used by the byte
alignment circuit to align the received serial data back to its original byte boundary. The decoder detects the
comma pattern in the K28.5 character, generating a synchronization signal aligning the data to their 10-bit
boundaries for decoding. It then converts the data back into 8-bit data. It is important to note that the comma can
be either a (B’0011111’) or the inverse (B’1100000’) depending on the running disparity. The TLK2226 decoder
will detect only the (B’0011111’) pattern. Therefore, since synchronization is achieved on the positive comma,
two consecutive K-codes containing commas are required to guarantee byte boundary synchronization (see
Table 3 Valid K characters for K-codes containing positive commas).
During all operations, the TLK2226 receive clocks (RCLKx) are a constant duty cycle and frequency. There are
no stretched nor shortened clock pulses.
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