TLK2226_09 Datasheet, PDF (13/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
www.ti.com
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
SIGNAL TERMINAL DESCRIPTION (continued)
SIGNAL
RDA[4:0]
LOCATION
TYPE
D9, C8, C7, B7, HSTL Output
A8
RDB[4:0]
A2, D3, C3, B4, HSTL Output
A4
RDC[4:0]
F4, F3, E4, E3, HSTL Output
E2
RDD[4:0]
J4, J3, K4, K3, HSTL Output
K2
RDE[4:0]
P2, L3, M3, N4, HSTL Output
P4
RDF[4:0]
L9, M8, M7, N7, HSTL Output
P8
Management Data Interface Signals
MDIO
F2
LVCMOS I/O
with P/U
MDC
F1
LVCMOS with
P/U
DVAD[4-3]
K9, K8
LVCMOS Input
with P/D
JTAG Interface Signals
TCK
G3
LVCMOS input
TDI
G4
TDO
H4
LVCMOS Input
with P/U
LVCMOS
Output
TMS
H3
TRSTN
G5
Miscellaneous Signals
CODE
E6
ENABLE
E9
LVCMOS Input
with P/U
LVCMOS Input
with P/U
LVCMOS Input
with P/U
LVCMOS Input
CTC_EN
H5
TCLKSEL
E8
RESET
E10
LPBK
E5
LVCMOS Input
with P/U
LVCMOS Input
with P/D
LVCMOS Input
with P/D
LVCMOS Input
with P/D
DESCRIPTION
Receive Data Channel A.
RTBI/RGMII mode:
Output data is aligned to the rising and falling edge of the RCLKA. Channel
data is output low-order bits first aligned to the rising edge of RCLKA
followed by high order bits aligned to the falling edge. These pins are
internally series terminated to provide direct connection to a 50-Ω
transmission line.
Receive Data Channel B
Receive Data Channel C
Receive Data Channel D
Receive Data Channel E
Receive Data Channel F
Management Data I/O. MDIO is the bi-directional serial data path for the transfer of
management data to and from the protocol device.
Input Management Data Clock. MDC is the clock reference for the transfer of
management data to and from the protocol device.
Management Address. Device Address: DVAD[4:3] is the externally set physical
address given to this device used to distinguish one device from another.
Test Clock. IEEE1149.1 (JTAG) TCK is used to clock state information and test
data into and out of the device during the operation of the test port.
Test Data Input. IEEE1149.1 (JTAG) TDI is used to serially shift test data and test
instructions into the device during the operation of the test port.
Test Data Output. IEEE1149.1 (JTAG) TDO is used to serially shift test data and
test instructions out of the device during operation of the test port. When the JTAG
port is not in use, TDO is in a high impedance state.
Test Mode Select. IEEE1149.1 (JTAG) TMS is used to control the state of the
internal test-port controller.
JTAG Reset. IEEE1149.1 (JTAG) TRSTN is used to reset the internal JTAG
controller.
PCS Functions Enable. When high, the Physical Coding Sublayer (PCS) functions
are enabled. This pin is logically AND'd with MDIO register PCS_EN.
Device Enable. Pulling this pin high will enable all outputs of the device. A low on
this pin will tri-state all outputs of the device, and causes the serial outputs to be
pulled to VDDA through 500 Ω. This signal must be externally held high during
JTAG manufacturing test on the customer application board. See Appendix A for
more details.
CTC Enable. This pin is AND'd with the CTC register bit. Setting this pin to logic 1
activates the CTC FIFO. A low on this pin disables the clock tolerance compensation
function. This function should only be activated in transceiver mode (CODE=1).
Independent Channel Transmit Clock Select. A logic 0 selects latching of all
channels synchronous to TCLKC. A logic 1 selects individual clocking. This pin bit is
logically OR'd with the TCLKSEL input MDIO register bit.
Chip Reset (FIFO Clear) Pulling this terminal high re-centers the transmit skew
buffers, receive channel synchronization FIFO's, and will reset MDIO flags to default
settings. Reset should be asserted for 100 µs after all power supplies and input
clock frequencies are within specification. Alternatively, a soft reset could be issued
after clock and power stabilization.
Loopback Enable. When set high, TX+/– outputs are pulled to VDDA through 500
ohms. The serial TX+/– output data is internally looped to RX+/– inputs. External
data applied to RX+/– inputs is ignored.
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