TLK2226_09 Datasheet, PDF (14/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
SIGNAL TERMINAL DESCRIPTION (continued)
SIGNAL
PRBSEN
LOCATION
F5
TYPE
LVCMOS Input
with P/D
SYNCEN
K10
SWAP
K7
REPEATA
K5
LVCMOS Input
with P/U
LVCMOS Input
with P/D
LVCMOS Input
with P/D
REPEATB
K6
LVCMOS Input
with P/D
RSVD
J5
RESERVED
SGMII
E7
LVCMOS Input
with P/D
Power and Reference Pins
VDDQ
B3, B6, B9, D5, Supply
D8, L5, L8, N3,
N6, N9
VDD
F10, G10, G11, Supply
H10, H11, J10
VDDS
G1, J2
Supply
VDDA
A11, B11, C11,
D11, E11, E12,
F11, J11, K11,
K12, L11,M11,
N11, P11
Supply
VREF
G2
Reference
GNDA
A14, B14, C14,
D14, E13, E14,
F14, G14, H14,
J14, K13, K14,
L14, M14, N14,
P14
Ground
GND
B2, B5, B8, D4,
D7, F6, F7, F8,
F9, G6, G7, G8,
G9, H2, H6, H7,
H8, H9, J1, J6,
J7, J8, J9, L4,
L7, N2, N5, N8
Ground
DESCRIPTION
PRBS Enable. When this terminal is asserted high, the pseudo-random bit stream
generator and comparator circuits are inserted into the transmit and receive data
paths on all channels, respectively.
If this pin is not used it can be tied to the GND reference. TX+– are transmitting 2⁷-1
PRBS bit streams. RX+– are comparing incoming data to 2⁷-1 PRBS bit stream.
Results of the RX comparison can be read from the MDIO.
SYNC Enable. When enabled, the TLK2226 byte-aligns incoming data on RX+/– on
positive RD (running disparity) commas (001 1111b). This pin is AND'd with the
COMM_DET register bit.
Parallel Port Swap. When enabled, the parallel port for channel B is routed to the
serial port for channel A, and the parallel port for channel A is routed to the serial
port for channel B. Likewise, the parallel ports for channels C and D, E and F are
swapped. This pin is logically OR'd with the PORT_SWAP register bits.
Repeater Mode Ports A, C, E. When enabled, the serial data on the channel B
receiver pins is repeated out on the channel A serial transmit pins. Likewise,
Channel D serial receive data is repeated out on channel C serial transmit pins, and
Channel F serial receive data is repeated out on channel E serial transmit pins.
This pin is logically OR'd with the REPEATER register bits for channels A, C, and E.
Repeater Mode Ports B, D, F. When enabled, the serial data on the channel A
receiver pins is repeated out on the channel B serial transmit pins. Likewise,
Channel C serial receive data is repeated out on channel D serial transmit pins, and
Channel E serial receive data is repeated out on channel F serial transmit pins.
This pin is logically OR’d with the REPEATER register bits for channels B, D, and F.
Reserved: This signal is reserved for TI internal testing. These should be connected
to GND in customer applications.
SGMII Mode When asserted, enables SGMII mode. When low, SGMII mode is
deasserted. This pin sets the default value of the SGMII register bit (16.4) on the
falling (deasserting) edge of the RESET pin.
HSTL I/O Supply Voltage. 1.5 V or 1.8 V
Digital Logic Power: Provides power for all digital circuitry. Nominally 1.8 V.
Secondary voltage LVCMOS I/O Supply Voltage 1.8 V OR 2.5 V OR 3.3 V
Analog Power. VDDA provides a supply reference for the high-speed analog
circuits, receiver and transmitter. Nominally 1.8 V.
Voltage Reference– for HSTL reference
Analog Ground. GNDA provides a ground reference for the high-speed analog
circuits, RX and TX.
Digital Logic Ground. Provides a ground for the logic circuits and digital I/O
buffers.
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