TLK2226_09 Datasheet, PDF (25/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
www.ti.com
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
4 TLK2226 devices connected to the same MDIO bus. The address of the individual device is set by the pins
DVAD[4:3]. PHYAD[4:3] correspond to DVAD[4:3] and is used to select the device. In order to read/write
information from/to the IEEE defined registers for a specific channel within TLK2226, PHYAD[2:0] are to be used
in the PHY Address section. Channel A would be addressed by setting PHYAD[2:0] to 3’b000, Channel B would
be addressed by setting PHYAD[2:0] to 3’b001 and so on.
IEEE defined registers (from 0x00 to 0x08 and 0x0F) are duplicated for each individual channel of TLK2226.
Whether or not additional registers are specific to a single channel or to all channels is lined out in the register
map below.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference (MDC).
The timing required to read from the internal registers is shown in Figure 21. The timing required to write to the
internal registers is shown in Figure 22.
MDC
MDIO
High
Z
32 ”1”s
0
1
1
0
A4
A0
R4 R0
0
D15
D0
Preamble
SFD
Read
Code
PHY
Address
Register
Address
Turn
Around
Data
Idle
Figure 21. Management Interface Read Timing
MDC
MDIO
32 ”1”s
0
1
0
1
A4
A0
R4 R0
1
0
D15
D0
Preamble
SFD
Write
Code
PHY
Address
Register
Address
Turn
Around
Data
Idle
Figure 22. Management Interface Write Timing
The MDIO Interface allows up to 32 (16-bit) internal registers. Sixteen registers are defined by the IEEE 802.3
Clause 22 specification. Additional registers are allowed for expanded functionality. The TLK2226 employs all
IEEE defined registers for PCS layer devices. The TLK2226 also implements additional registers for expanded
functionality. The IEEE defined registers and the expanded functionality registers are outlined in Table 5.
All latching bits need to be read twice after device initialization to read current/correct status.
The legend for the register map summary is:
1. Self Clearing
2. ReadWrite
3. Read Only
4. Latched High
5. Latched Low
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