TLK2226_09 Datasheet, PDF (5/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

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LVCMOS ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
V_OL Low-level output voltage
V_IH High-level input voltage
V_IL
Low-level input voltage
I_H
High input current
I_L
Low input current
C_IN Input capacitance
TEST CONDITIONS
I_OL = 1 mA, V_DDS = MIN
V_DDS = 1.8 V
V_DDS = 2.5 V
V_DDS = 3.3 V
V_DDS = 1.8 V
V_DDS = 2.5 V
V_DDS = 3.3 V
V_DDS = MAX, V_IN = 2.0 V
V_DDS = MAX, V_IN = 2.0 V
TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
MIN
0
1.4
1.55
2.0
–0.2
–0.2
–0.2
TYP
0.25
MAX
0.5
V_DDS +0.2
V_DDS +0.2
V_DDS +0.2
0.63
0.7
1.4
400
–600
4
UNIT
V
V
V
µA
µA
pF
HSTL ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
V_OH(dc)
V_OL(dc)
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
I_IH
I_IL
I_OH(dc)
I_OL(dc)
C_IN
PARAMETER
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
High input current
Low input current
High output current
Low output current
Input capacitance
TEST CONDITIONS
DC output, logic high
DC output, logic low
DC input, logic high
DC input, logic low
AC input, logic high, V_DDQ = 1.5 V
AC input, logic high, V_DDQ = 1.8 V
AC input, logic low, V_DDQ = 1.5 V
AC input, logic low, V_DDQ = 1.8 V
Receiver only
V_DDQ = 1.5 V
V_DDQ = 1.5 V
MIN
V_DDQ–0.4
V_REF+0.10
–0.5
V_REF+0.20
V_REF+0.35
–8
8
TYP
MAX
V_DDQ
0.4
V_DDQ+0.3
V_REF–0.10
UNIT
V
V
V
V
V
V_REF–0.20
V
V_REF–0.35
±10 µA
mA
mA
4 pF
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)⁽¹⁾
over recommended operating conditions (unless otherwise noted)
PARAMETER
R_ω
Frequency
Accuracy
Duty cycle
Jitter
TEST CONDITIONS
Minimum data rate
Maximum data rate
Random and deterministic
MIN
TYP–0.01%
TYP–0.01%
–100
40%
NOM
125
125
50%
MAX
TYP+0.01%
TYP+0.01%
100
60%
40
UNIT
MHz
MHz
ppm
ps_pp
(1) This clock should be crystal referenced to meet the requirements of this table ( Contact TI for specific clocking recommendations). Rate
activity of REFCLK is internally monitored. As soon as REFCLK is disconnected the device will initiate a global power-down mode; PLLs
will be turned off, output divers disabled and other current sources such as pull-up’s and pull down’s will be disabled to avoid power
consumption. To re-activate the device, restart REFCLK.
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