TLK2226_09 Datasheet, PDF (20/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
Transmit Parallel Interface
In synchronous channel mode, parallel data to be transmitted is latched by both the rising and falling edges of
TCLKC. TCLKC must be frequency synchronous with REFCLK (0 ppm), but may have any phase relationship
with respect to REFCLK. While in synchronous channel mode, it is recommended that the unused individual
channel clocks TCLKx be grounded to minimize noise.
In independent channel mode, parallel data to be transmitted on channel A is latched on the rising and falling
edges of TCLKA. The transmit data bus for channel B is latched on the rising and falling edges of TCLKB, the
transmit data bus for channel C is latched on the rising and falling edges of TCLKC and so on.
tPULSE
TCLKx
tr
VDDQ/2
tf
tSETUP
tHOLD
tSETUP
tHOLD
TDx[4:0]
LSB Nibble
MSB Nibble
Figure 19. Transmit Timing (Clock Centered)
Serializer
The parallel-to-serial shift register on each channel takes in an internally generated 10-bit wide word from either
the 8b/10b encoders, if enabled, or directly derived from the 5-bit to 10-bit converter and converts it to a serial
stream. The shift register is clocked by the internally generated bit clock, which is 10 times the reference clock
(REFCLK) frequency. The least significant bit (LSB) for each channel is transmitted first.
Serial Output Drivers
The TLK2226 serial transmitter utilizes a Voltage Mode Logic (VML) driver that drives both the high level and
low level of the output signal swing. Thus, no external pull-up resistors are needed as in the case of Current
Mode Logic (CML) drivers, nor are pull-down resistors needed as in the case of Emitter-Coupled Logic (ECL).
The output voltage swing is set at a nominal 800 mV on each leg of the differential signal, making the output
signal swing compatible with PECL systems.
The TLK2226 output driver has a pre-emphasis option (selectable through MDIO) for improved performance
over lossy media such as backplane traces.
RECEIVE DATA PATH
The receiver input data must be ac-coupled and have a rate of 1.0–1.3 Gbps (or 1/10^th that rate for 100FX
mode). Resistive termination is implemented on-chip to match 50Ω.traces. The clock recovery circuitry retimes
the input data by extracting a clock from the input data, and passes on the serial data and this recovered clock
to the deserializer. Byte alignment is performed on K-characters per IEEE 802.3z while in 1.25Gbps operation
(see byte alignment logic section for details). Byte alignment is performed on the NRZI Encoded IDLE pattern
while in 125Mbps mode.
Serial Input Samplers
The TLK2226 strobes the received serial data with an internal high-speed clock that is locked to the data stream
by the clock recovery function. The differential serial receive data buffers internally terminate the transmission
line with 50Ohm termination resistors. It is expected that the serial receive data is AC coupled, so the internal
termination also biases the signal to the common mode level that is optimum for the input samplers. No external
components are needed apart from the AC coupling capacitors themselves
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