TLK2226_09 Datasheet, PDF (22/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
Table 3. Valid K Characters
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K CHARACTER
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
RECEIVE DATA BUS
000 11100
001 11100
010 11100
011 11100
100 11100
101 11100
110 11100
111 11100
111 10111
111 11011
111 11101
111 11110
ENCODED K-CODE
NEGATIVE RUNNING
DISPARITY
POSITIVE RUNNING
DISPARITY
001111 0100
110000 1011
001111 1001⁽¹⁾
110000 0110
001111 0101
110000 1010
001111 0011
110000 1100
001111 0010
110000 1101
001111 1010⁽²⁾
110000 0101
001111 0110
110000 1001
001111 1000⁽²⁾
110000 0111
111010 1000
000101 0111
110110 1000
001001 0111
101110 1000
010001 0111
011110 1000
100001 0111
(1) Setting COMMA_DET=0, or SYNCEN pin K10 by changing its value via MDIO 17.8 would disable
comma detection, and byte alignment would take place on any bit boundary; this permits external byte
alignment on different bit sequences, and allows for the use of different bit balancing algorithms.
(2) A comma is contained within this K-code.
Receive Parallel Interface
The receive data bus for all channels may be output in either a source-centered fashion (with the bus clock
transitions in the center of the data eye) or a source-aligned fashion (with the bus clock transitions aligned to the
data transitions) allowing direct connection to the protocol device.
Parallel data to be transferred to the protocol device is output referenced to both the rising and falling edges of
RCLKx. RCLKx is frequency synchronous with REFCLK when the Clock Tolerance Compensation logic is
enabled, but RCLKx has no set phase relationship with respect to REFCLK. Each channel is output on RDx[4:0]
respectively, as shown in Figure 20.
Parallel data to be transferred to the protocol device on channel A (RDA[4:0]) is output referenced to both the
rising and falling edges of the RCLKA, Channel B (RDB [4:0]) is output referenced to both the rising and falling
edges of RCLKB. Channels C through F are output in the same fashion with their respective clocks. Nibble
ordering is such that least significant bits are output first and on the rising edge of the clock.
It is important to note, that when the Clock Tolerance Compensation logic is enabled, all recovered byte clocks
(RCLKx) are buffered versions of REFCLK. When the Clock Tolerance Compensation circuit is disabled, the
RCLKx for a channel will be the true 1/10^th rate clock recovered from the incoming data stream. Like transmit
timing options, receive clocks RCLKx are either Source Centered or Aligned meeting specified output setup and
hold times. Clock Tolerance Compensation is only available in RGMII mode.
RCLK[A−F]
tr
RDx[4:0]
VDDQ/2
tf
t SETUP
tHOLD
t SETUP
tHOLD
LSB Nibble
MSB Nibble
Figure 20. RTBI Receive Timing (Clock Centered)
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