TLK2226_09 Datasheet, PDF (8/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SLLS689D–JANUARY 2006–REVISED DECEMBER 2006
+1000
+200
0
−200
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _−1000
Receive
0.3
0
0.7
1.0
Normalized Time
Figure 5. Receive Template
J _DR
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J_R
J_R
J _TOL
NOTE: J_TOL = J_R + J_DR, where J_TOL is the receive jitter tolerance, J_DR is the received deterministic jitter, and J_R is the
Gaussian random edge jitter distribution at a maximum BER = 10^-12.
Figure 6. Input Jitter
HSTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
T_r
Clock and data rise time
T_f
Clock and data fall time
T_OSU
T_OHD
T_suav
T_hdav
RD[4:0] valid (setup) prior to RCLK
transition high or low
RD[4:0] valid (hold) after RCLK transition
high or low
RCLK transition high or low to data valid
window beginning (RD[4:0]).
RCLK transition high or low to data valid
window ending (RD[4:0]).
TEST CONDITION
80% to 20% output voltage, see Figure 7,
C = 10 pF
80% to 20% output voltage, see Figure 7,
C = 10 pF
See Figure 7, timing relative to 0.5×VDDQ,
25 MHz and 125 MHz
See Figure 7, timing relative to 0.5×VDDQ,
25 MHz and 125 MHz
See Figure 8, timing relative to 0.5×VDDQ, 25
MHz and 125 MHz
See Figure 8 , timing relative to 0.5×VDDQ,
25 MHz and 125 MHz
MIN NOM MAX UNIT
1.5 ns
1.8 ns
1.2
ns
1.2
ns
800 ps
3.2
ns
RCLK[A−F]
tr
RDx[4:0]
VDDQ/2
tf
tOSU
tOHD
t OSU
tOHD
LSB Nibble
MSB Nibble
Figure 7. HSTL Receive Output Timing Requirements (Centered)
8
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