TLK2226_09 Datasheet, PDF (18/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
RGMII PORT-SWAP MODE
The TLK2226 provides a set of multiplexors on the parallel busses between pairs of channels such that the
RGMII port for Channel A can be steered to the serial port for Channel B, while at the same time the RGMII port
for Channel B can be steered to the serial port for Channel A. See Figure 18 for the block diagram illustrating
this mode. Likewise, the RGMII ports for channels C and D may be swapped, as may the RGMII ports for
Channels E and F,
The selection of swapping a pair of RGMII ports is accomplished by setting the appropriate register bit in MDIO
register space.
RX RGMII A
TX RGMII A
TX RGMII B
RX RGMII B
5bit DDR
to
10bit
SDR
Interface
5bit DDR
to
10bit
SDR
Interface
PCS
Logic
PCS
Logic
CTC
function
and
8b10
coding
CTC
function
and
8b10
coding
channel A
TX Analog
Core
channel B
RX Analog
Core
channel A
channel B
2 of the 6 channels of TLK2226 shown
data path for RGMII mode (with port swapping)
Figure 18. RGMII Mode with Port Swapping
+
TXA_{_}
+
_^RXA
+
RXB
_
+
TXB_{_}
100FX 125Mbps MODE
The TLK2226 can be set to operate at 125 Mbps on a per channel basis. While in 100FX mode, the PCS
functions are enabled for RGMII mode, but the transmit and recovered byte clocks are at 25 MHz. When a
channel is in 100FX mode the PCS functions for that channel will comply with the IEEE802.3 100 base-x
specifications, including the 4b/5b coding, NRZI Encoding, and nibble alignment.
While a channel is in 100FX mode, the reference clock for that channel will still be the 125MHz reference clock
input for the TLK2226. For this reason, the transmit clock for that channel’s RGMII port must be a 25MHz
derivative of the reference clock without any ppm frequency offset. The recovered byte clock for that channel’s
RGMII port will be divided down to 25 MHz.
Auto rate select for a channel will operate primarily off of transition density of the incoming serial data stream.
The Clock and Data Recovery (CDR) function of the channel receiver will always operate at the 1.25Gbps rate.
If the incoming data stream is properly coded 8b/10b data for 1.25Gbs data then the transition density of the
incoming data will be detected and that channel will operate at 1.25Gbps. If properly 4B/5B and NRZI Encoded
data for 100FX operation received, then the incoming transition density will be detected as a maximum 1
transition per 10bit input word, and that channel will operate at 125 Mbps. When a channel is operating at
125Mbps, the actual SERDES front end will still be operating at 10 times that rate by transmitting every 100FX
bit 10 times in a row and by over-sampling every incoming 100FX bit by a factor of 10.
SGMII (Serial GMII) (1000 Mbps/100 Mbps/ 10 Mbps) MODE
The TLK2226 can be set to operate in SGMII mode (register bit 16.4). In this mode, the serial side of TLK2226
always operates at 1.25 Gbps. The parallel interface speed is directly selected through mdio register bits 0.6 and
0.13. In 10 Mbps mode, the parallel interface runs at 2.5 MHz. In 100 Mbps mode, the parallel interface runs at
25 MHz. In 1000 Mbps mode, the parallel interface runs at 125 MHz. In all three modes, the slightly modified
(per the SGMII document) auto-negotiation state machine (if enabled) is active.
In 1000 Mbps SGMII mode the parallel interface operates identical to the 1000Base-X case with SGMII disabled.
In both 10 and 100 Mbps SGMII modes, the parallel data is transferred on the parallel interface at the lower
provisioned rate, and replicated either 10 or 100 times for transmission (and deleted accordingly in the receive
direction) by the PCS layer out the serial interface. Note that in both the transmit and receive directions for both
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