TLK2226_09 Datasheet, PDF (32/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
Table 17. (Vendor Specific) CH Control Register 0 (0x10) Bit Definitions
Bit(s) Default Value
Name
16.15 1B’0
Global write
16.14 1B’1
16.13 1B’1
16.12 1B’1
16.11 1B’0
TX Amplitude
Control
CTC Enable
PCS Enable
Swap Enable
16.10 1B’0
16.9 1B’0
16.8 1B’0
Repeat Enable
Serial Shallow
Loopback
Farend Loopback
16.7 1B’0
PRBS Verifier
Enable
16.6 1B’0
PRBS Enable
16.5 1B’1
Rate Sense
Enable
16.4 SGMII Pin Value SGMII Mode
at Rising Edge of Enable
RESET.
16.3 1B’0
TCLK Select
16.2 1B’1
Comma Detect
Description
Read/Write
When written as 1 the settings in 16.14:0 will affect all channels of one
device simultaneously.
When written as 0 the settings in 16.14:0 are only valid for the
addressed channel. This value always reads zero.
Read/Write
Self Clearing
1 = Transmitter Amplitude is at full value.
0 = Transmitter Amplitude is half value.
This should be set to 0 during SGMII mode.
Read/Write
Logically AND'd with the CTC_EN pin.
0 = clock tolerance compensation is disabled
1 = CTC is enabled (default)
Read/Write
Logically AND'd with the CODE pin.
0 = PCS functions are disabled
1 = PCS functions are enabled (default)
Read/Write
When logic high the parallel interfaces of two adjacent channels are
swapped. For example data coming in at TDA will be sent out at TXB.
Data coming in at RXA will be sent out at RDB in this example.
Read/Write
This bit is always valid for a channel pair like AB, CD, or EF.
Logically OR'd with the SWAP pin.
0 = Swap function disabled.
1 = Swap function enabled.
When logic high the channel will ignore the data presented to its transmit Read/Write
parallel interface but will send the data coming in at the serial receive
interface of its partner channel.
The partner channel is the other one of the pair AB, CD, or EF.
Logically OR'd with REPEATA or REPEATB pins.
Applicable only when standard loopback bit (Register 0.14) is low and
the external loopback pin (LPBK) is low.
Read/Write
When asserted high the data presented at the parallel transmit interface
is looped back to the parallel receive interface of the same channel.
0 = Serial shallow loopback is disabled.
1 = Serial shallow loopback is enabled.
When asserted high the data presented at the serial receive interface is
looped back to the serial transmit interface of the same channel via the
deserializer, the serializer and if enabled the PCS function. If 1GX PCS
is not enabled (i.e. RTBI or 100Base-FX modes), the incoming data rate
must be frequency locked (ppm 0) with REFCLK.
Read/Write
Also referred to as remote loopback.
0 = Farend Loopback is disabled.
1= Farend loopback is enabled.
A logic 1 enables the PRBS verifier in the receive data path.
Read/Write
Logically OR'd with the PRBSEN pin.
A logic 1 enables the PRBS generator in the transmit data path.
Logically OR'd with the PRBSEN pin.
A logic 1 will enable auto rate sensing between 1.25 Gbps data and 125
Mbps data.
When set to 1, enables SGMII mode.
When set to 0 (default), disables SGMII mode.
When set to 1, the standard based bits 0.6 and 0.13 directly determine
the parallel data rate of operation, according to the “Per Channel Rate
Determination” table.
Logically OR'd with the TCLKSEL pin.
0 = parallel transmit data is latched synchronous to TCLKC (default)
1 = parallel transmit data is latched synchronous to TCLK of the
according channel.
A logic 1 enables the comma detection in the serial receive circuit.
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
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