TLK2226_09 Datasheet, PDF (44/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
Per Channel Loopback Definitions
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PCS Transmit
SERDES Transmit
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PCS Receive
SERDES Receive
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Deep Loopback
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Shallow Loopback
Far End (Remote) Loopback
Figure 23. Per Channel Loopback Definitions
Power-On Reset
Upon application of minimum valid power, the TLK2226 generates an internal power-on reset. During the
power-on reset the receive data outputs are tri-stated. The length of the power-on reset cycle is dependent upon
the power supply’s ramp curve. The power-on reset is sourced by the digital core supply voltage VDD.
PRBS generator and comparator
The TLK2226 has a built-in 27-1 PRBS (Pseudo Random Bit Stream) self test function available on each
channel. Compared to all 8B/10B data pattern combinations, the PRBS is a worst-case bit pattern. The self-test
function is enabled using the PRBSEN pin or setting the PRBS Enable bit in the MDIO registers. When the
self-test function is enabled, a PRBS is generated and fed into the 10-bit parallel-to-serial converter input
register. Data on the Transmit Data Bus inputs to the TLK2226 are ignored during the PRBS test mode. The
PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter.
The output can be sent to a BERT (Bit Error Rate Tester) or the receiver of another TLK2226 channel.
Setting the PRBSEN pin has the following effect:
A PRBS datastream is generated on the TX ±ports.
The RX ± ports expect PRBS pattern at their inputs and status signals could be monitored on RD bus or
MDIO. While the PRBS test function is in operation, a real-time signal PRBS_PASS is available on RDx[1]
or RDx[2] of partnering channel depends on whether the rate is 1.25 Gbps or 125Mbps; other signals on the
RDx[4:0] busses have no meaning during PRBS testing. Alternately, the result can be read from the MDIO
vendor specific register 29 and 31. Register 29 is the error counter for high speed(1.25Gbps) PRBS Verifier.
Register 31 is the error counter for low speed(125Mbps) PRBS. These are counters that increment by one
for each received character that has error. Reading the MDIO register clear the counter information in the
MDIO.
The PRBS test function can also be activated through MDIO by activating the PRBS_EN Register 16.7:6.
The PRBS function can be used in conjunction with the serial loopback function. This can be done by asserting
the PRBS generators via the PRBSEN pin or MDIO register 16.7:6, and assertion of the LPBK pin or loopback
control provided via MDIO register 0.14. The result from PRBS verification at the RX ports of the device can be
read from the MDIO registers 29 and 31.
Simultaneous assertion of the PRBS_EN and PRBS_VE register bits in MDIO register 16.7:6, and the serial
loopback enable, puts the device in a test mode which provides PRBS generation and verification at the local
transmitter and receiver internal to the TLK2226
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