TLK2226_09 Datasheet, PDF (43/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
www.ti.com
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
PRBS GENERATION AND VERIFICATION PROCEDURE
• Issue a hard or soft reset
• Write a zero to 0.12 (disable auto-negotiation).
• Write a zero to 16.5 (disable auto rate sense enable).
• Write a one to 0.6 (1000Base-X rate) or zero to 0.6 (100Base-FX rate).
• Write a zero to 0.13 (1000Base-X rate) or one to 0.13 (100Base-FX rate).
• Write “0” to the PCS Enable bit (bit 12) of the Channel Control_0 register (Reg 16) to disable PCS function.
• Write “0” to Comma Detect bit (bit 2) of the Channel Control_0 register (Reg 16) to disable comma detect
function.
• Write “1” to the PRBS Generator Enable (bit 6) field of the Channel Control_0 register (Reg 16) to enable
PRBS generator.
• For 1000Base-X mode, Read the PRBS high speed test error counter (Reg 29) to clear the counter
• For 100fx mode, Read the PRBS low speed test error counter (Reg 31) to clear the counter
• Write “1” to the PRBS Verifier Enable (bit 7) fields of the Channel Control_0 register (Reg 16) to enable
PRBS verifier
• At this point the pattern verification is in progress
• Errors are reported in PRBS high speed test error counter (Reg 29) for 1000Base-X and PRBS low speed
test error counter (Reg 31) for 100fx mode.
• Reading the counters has no effect on the test except clearing the counters, i.e. the verification of the pattern
continues until the PRBS Generator/PRBS Verifier Enable (bit 7:6) of the Channel Control_0 register (Reg
16) is cleared
TESTABILITY
Serial Loopback (Shallow and Deep)
The TLK2226 can provide a self-test function by enabling the internal loop-back path for all channels with the
assertion of LPBK. The loopback for individual channels can be enabled via the MDIO registers or for all
channels through the LPBK pin. The parallel data output can be compared to the parallel input data for that
channel to provide functional verification. The external differential output is held in a high-impedance state
(pulled to VDDA through 500 Ω) during deep loop-back testing. Loopback for all channels (called deep loopback)
may be enabled by assertion of the LPBK pin (putting all channels into deep loopback simultaneously) or setting
register bit 0.14 (on an individual channel basis). This causes transmit serial data from a channel to be input on
the serial input for that channel, testing the entire path of the serializer/deserializer (except the output
driver/receiver).
Shallow loopback may be enabled by setting the shallow loopback register bit 16.9. This will loop the parallel
transmit data bus for an individual channel to the parallel receive bus on that channel.
Far-End Loopback
The TLK2226 can provide a self-test function by enabling the internal far end loop-back (also referred to as
remote loopback) path for a channel with the assertion of MDIO register bit 16.8. The serial data output can be
compared to the serial input data for selected channels to perform functional verification of high speed RX and
TX. The parallel input data during far end loopback test are disregarded. The external parallel outputs are
optionally in a high-impedance state via MDIO control bit (0.10).
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