TLK2226_09 Datasheet, PDF (42/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
JITTER TEST PATTERN GENERATION AND VERIFICATION
Use one of the following procedures to generate and verify the respective jitter test pattern:
• High/Mixed/Low Frequency Test Pattern:
– Issue a hard or soft reset
– Write a zero to 0.12 (disable auto-negotiation).
– Write a zero to 16.5 (disable auto rate sense enable).
– Write a one to 0.6 (1000Base-X rate).
– Write a zero to 0.13 (1000Base-X rate).
– Write “0” to the PCS 1Gx Rx Enable bit (bit 2) of the Channel Control_1 register (Reg 17) to disable
decoder/ PCS 1Gx RX function.
– Write “0” to Comma Detect bit (bit 2) of the Channel Control_0 register (Reg 16) to disable comma detect
function.
– Write “000” to the Pattern_select(bit 2:0) field of the Test Pattern Control register (Reg 20) to select high
frequency test pattern, or “001” to select the low frequency test pattern, or “010” to select the mixed
frequency test pattern. .
– Write “1” to the Generator Enable (20.4).
– Read the test pattern error counter register(Reg 22) for the channel to clear the counters.
– Write “1” to the Verifier Enable (20.3)
– In order for the Test Pattern Verifier to start checking the test pattern, it has to achieve sync to the test
pattern. To make sure that the test pattern checking has started, read bit 1(Test pattern sync) of Test
pattern Sync Status (Reg 21) register. Make sure that the Fixed Test Pattern Sync bit is HIGH for the
corresponding lane. If the sync status is not high, this indicates that the verifier never achieved sync,
which may indicate a more severe link problem.
– At this point the pattern verification is in progress
– Errors are reported in the error counter at Test Pattern Counter Register (Reg 22).
– Reading the counters has no effect on the test except clearing the counters, i.e. the verification of the
pattern continues until the test pattern enable bit(bit 4) of the Test Pattern Control register(Reg 20) is
cleared.
• Long/Short Continuous Random Test Pattern (Long/Short CRPAT
– Issue a hard or soft reset
– Write a zero to 0.12 (disable auto-negotiation).
– Write a zero to 16.5 (disable auto rate sense enable).
– Write a one to 0.6 (1000Base-X rate).
– Write a zero to 0.13 (1000Base-X rate).
– Write “011” to the Pattern_select(bit 2:0) field of the Test Pattern Control register (Reg 20) to select
CRPAT Long test pattern, or “100” to select the CRPAT Short test pattern.
– Write “1” to the Generator Enable (20.4).
– Read the CRPAT Error Counter_1 register and CRPAT Error Counter_2 register (Reg 23 & Reg 24) to
clear
– Write “1” to the Verifier Enable (20.3).
– In order for the Test Pattern Verifier to start checking the test pattern, it has to receive the Preamble /SFD
that is sent at every packet from the test pattern generator. To make sure that the test pattern checking
has started, read bit 0 of the Test Pattern Sync Status Register(Reg 21). Make sure that the CRPAT Sync
bit is HIGH. If the sync status is not high, this indicates that the verifier never received the Preamble,
which may indicate a more severe link problem.
– At this point the pattern verification is in progress. Perform the test as long as desired.
– Read the MSB of the error counter by reading CRPAT Error Counter_1 (Reg 23), then read the LSB of
the error counter at CRPAT Error Counter_2 (Reg 24). If user reads register 24 without reading register
23 first, the count value read through 24 may not be correct.
– If another test is to be performed go to the first step
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