TLK2226_09 Datasheet, PDF (12/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
SIGNAL TERMINAL DESCRIPTION
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SIGNAL
LOCATION
TYPE
Serial I/O Signals
TXA+, TXA–
TXB+, TXB–
TXC+, TXC–
TXD+, TXD–
TXE+, TXE–
TXF+, TXF–
A13, A12,
D13, D12,
F13, F12,
J13, J12,
L13, L12,
P13, P12
VML Output
RXA+, RXA–
RXB+, RXB–
RXC+, RXC–
RXD+, RXD–
RXE+, RXE–
RXF+, RXF–
B13, B12,
C13, C12,
G13, G12,
H13, H12,
M13, M12,
N13, N12
PECL-
compatible
Input
Transmit Data Bus and Clock Signals
REFCLK
H1
LVCMOS Input
TCLKA,
A9,
TCLKB,
A5,
TCLKC,
C1,
TCLKD,
M1,
TCLKE,
P5,
TCLKF
P9
HSTL Input
TDA[4:0]
C9, D10, C10, HSTL Input
B10, A10
TDB[4:0]
C4, C5,
D6, C6, A6
HSTL Input
TDC[4:0]
D2, D1, C2, B1, HSTL Input
A1
TDD[4:0]
L2, L1, M2, N1, HSTL Input
P1
TDE[4:0]
M4, M5, L6, M6, HSTL Input
P6
TDF[4:0]
M9, L10, M10, HSTL Input
N10, P10
Receive Data Bus and Clock Signals
RCLKA
A7,
RCLKB
A3,
RCLKC
E1,
RCLKD
K1,
RCLKE
P3,
RCLKF
P7
HSTL Output
DESCRIPTION
Differential Output Transmit. TX[A-F]+ and TX[A-F]- are differential serial outputs
that interface to a copper or an optical I/F module. TX[A-F]+ and TX[A-F]- are pulled
to VDDA through 500 ohms when LPBK = high or when the LOOPBACK (deep only)
bit for a particular channel in the MDIO registers is set.
Differential input receive. RX[A-F]+ and RX[A-F]- are the differential serial input
interface from a copper or an optical I/F module. Differential resistive termination is
built-in for these terminals.
Reference Clock. REFCLK is an external input clock that provides the clock
reference.
Transmit Data Clock Channels A, B, C, D, E, and F.
RTBI/RGMII mode:
When in Independent Transmit channel mode (TCLKSEL = 1) these pins
are used to latch data for their respective channels on both the rising and
falling edges. TCLKA latches data for channel A. TCLKB latches data for
channel B. TCLKC latches data for channel C. TCLKD latches data for
channel D. TCLKE latches data for channel E. TCLKF latches data for
channel F.
When in synchronous transmit channel mode (TCLKSEL = 0) only TCLKC
is used as the transmit clock for all 6 parallel transmit busses.
Transmit Data Channel A.
RTBI/RGMII mode:
The parallel data is clocked into the transceiver on the rising and falling
edge of TCLKx and transmitted as a serial stream with TDx0 rising edge
data sent as the first bit. Data is input low-order bits first aligned to the rising
edge of TCLKx following by high order bits aligned to the falling edge.
Transmit Data Channel B.
Transmit Data Channel C.
Transmit Data Channel D.
Transmit Data Channel E.
Transmit Data Channel F
Individual Receive Byte Clock Channels A through F.
RTBI/RGMII mode:
Recovered byte clock for channels A through F. These clocks are used by
the protocol device to latch the received data output for channels A through
F. Data is aligned to both the rising and falling edges.
If the internal CTC FIFO is disabled for a channel, the clock for that channel
is 1/10^th the clock recovered from the incoming data stream. If CTC is
enabled for a channel, the clock for that channel is a buffered version of
REFCLK.
These pins are internally series terminated to provide direct connection to a
50-Ω transmission line.
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