TLK2226_09 Datasheet, PDF (28/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
Table 6. Control 1 Register (0x00) Bit Definitions
Bit(s) Default Value
0.15
1B’0
Reset
Name
0.14
1B’0
Loopback
0.13
1B’0
Speed Selection(LSB)
0.12
1B’1
0.11
1B’0
Auto-Negotiation Enable
Power Down
0.10
1B’0
0.9
1B’0
0.8
1B’1
0.7
1B’0
0.6
1B’1
Isolate
Restart Auto-Negotiation
Duplex Mode
Collision Test
Speed Selection (MSB)
0.5:0
6B’00 0000
Reserved
Description
Logically OR'd with the RESET pin.
1= Global Resets including FIFO clear
0= Normal operation (default)
Logically OR'd with LPBK pin. (Also referred to as deep
loopback)
1=enable loopback mode per channel
0=disable loopback mode per channel
This is the least significant bit of the speed selection bits
(MSB is 0.6).
{0.6,0.13} = 2’b10 1000Base-X Rate
{0.6,0.13} = 2’b01 100Base-FX Rate
{0.6,0.13} = 2’b00 10 Mbps (SGMII Mode Only)
TLK2226 will not allow writes of 2’b11 to {0.6,0.13}, since
it is an unsupported rate.
It allows the device to perform an Auto-Negotiation as
described in IEEE802.3 clause 37.
1= Auto-Negotiation enabled (default)
0= Auto-Negotiation disabled
Setting this bit high powers down the device, with
exception that MDIO interface stays active.
All zero’s are sent on the receive parallel interface when
this bit is set.
1 = Power Down mode is enabled.
0 = Normal operation (default).
Setting this bit high isolates the channel from the RGMII
interface. Inputs are ignored; Outputs are set to high
impedance.
1 = Isolate is enabled
0 = Normal operation (default)
Restarts an Auto-Negotiation sequence as described in
IEEE802.3 clause 37.
1= Restart Auto-Negotiation
0= Normal operation (default)
Only Full Duplex is supported. Write is ignored,
Read will return a ‘1’.
Not Applicable. Read will return a 0.
This is the most significant bit of the speed selection bits
(LSB is 0.13).
{0.6,0.13} = 2’b10 1000Base-X Rate
{0.6,0.13} = 2’b01 100Base-FX Rate
{0.6,0.13} = 2’b00 10 Mbps (SGMII Mode Only)
TLK2226 will not allow writes of 2’b11 to {0.6,0.13}, since
it is an unsupported rate.
Write is ignored and returns 0 when read.
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
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Read/Write
Read/Write
Self Clearing⁽¹⁾
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Self Clearing
Read Only
Read Only
Read/Write
Read only
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