TLK2226_09 Datasheet, PDF (36/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
Table 25. (Vendor Specific) CRPAT Error Counter2 (0x18) Bit Definitions
Bit(s)
Default Value
Name
24.15:0 16B’1111_1111_1111_1101 Reserved
Description
LSB of CRPAT Error Counter. This counter reflects errors
for CRPAT Test. Counter increments by one for each
received character that has an error. Counter clears upon
read.
Read/Write
Read Only Note:
Register 23 has
to be read first.
Table 26. (Vendor Specific) Descrambler Status (0x19) Bit Definitions
Bit(s)
25.15
25.14
1B’0
1’B0
Default Value
Name
Reserved
Sync_1GX
25.13:0 14B’000_0000_0000_0000 Reserved
Description
Read will return 0, writes will be ignored.
When low, indicates PCS synchronization has lost sync.
When high, indicates PCS synchronization is currently in
sync.
Read will return 0, writes will be ignored
Read/Write
Read Only
Read Only
Latched Low
Read Only
Table 27. (Vendor Specific) Scrambler/DLL control (0x1A) Bit Definitions
Bit(s)
26.15
26.14:11
26.10:8
Default Value
PG1.0 : 1’b1
PG2.0 : 1’b0
4B’0000
3B’000
26.7
26.6:4
1B’0
3B’000
26.3:0 4B’0100
Name
PG1.0 –vs- PG2.0
Reserved
TX DLL Offset[2:0]
Reserved
RX DLL Offset[2:0]
Reserved
Description
PG1.0 : Read/Write Default to One
PG2.0 : Read Only, Read will return 0
Read will return 0, writes will be ignored
Unit delay offset setting for TX DLL.
If [2] (MSB) is 1’b1, then delay can be increased by
[1:0] (LSB’s) unit delays.
If [2] (MSB) is 1’b0, then delay can be decreased by
[1:0] (LSB’s) unit delays.
Read will return 0, writes will be ignored
Unit delay offset setting for Rx DLL.
If [2] (MSB) is 1’b1, then delay can be increased by
[1:0] (LSB’s) unit delays.
If [2] (MSB) is 1’b0, then delay can be decreased by
[1:0] (LSB’s) unit delays.
Read will return 0, writes will be ignored
Read/Write
PG1.0 : Read/Write
PG2.0: Read Only
Read Only
Read/Write
Read Only
Read/Write
Read Only
Table 28. (Vendor Specific) Reserved Test Mode Control Registers (0x1B) Bit Definitions
Bit(s)
Default Value
27.15.12 4’B1111
Name
Test MUX Select
27.11 1’b0
Test MUX Enable
27.10:0 11B’000_0000_0000 Reserved
Description
Read/Write
Must be set to 4’B1010 to allow PRBS_PASS and
Read/Write
PRBS_SYNC to be output on the partner RD[1] and RD[2]
parallel interface pins.
When asserted, allows the test MUX data to be driven
Read/Write
onto the parallel interface (data from the partner channel).
Read will return 0, writes will be ignored
Read Only
Table 29. (Vendor Specific) Reserved Channel Status Registers (0x1C) Bit Definitions
Bit(s)
28.15
28.14
Default Value
1B’0
1’B1
28.13 1’B0
28.12 1’B0
28.11:0 12B’0000_0000_0000
Name
TI Test
Actual Channel Rate
Encoder Invalid Code
Word
Decoder Invalid Code
Word
Reserved
Description
Reserved for TI test
When high, indicates the serial side of the channel is
currently operating in 1.25 Gbps mode.
When low, indicates the channel is currently operating in
125 Mbps mode.
When high, indicates that the 1000Base-X encoder
received an invalid control word.
When high, indicates that the 1000Base-X decoder
received an invalid code word.
Read will return 0, writes will be ignored
Read/Write
Read Only
Read Only
Read Only
Latched High
Read Only
Latched High
Read Only
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