TLK2226_09 Datasheet, PDF (19/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
www.ti.com
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
10 and 100 Mbps SGMII modes, the nibble transferred on the rising edge is repeated on the negative edge of
the parallel interface clock. For a given packet byte, the lower nibble is placed on the parallel interface during the
first clock period (the data is duplicated on falling edge), followed by the upper nibble of the packet byte on the
next clock period (data is duplicated on the falling edge). Also note that the control bits for the byte are
duplicated according to the RGMII standard across the two clock periods.
All test related and data path functional modes for TLK2226 are capable of operating in the SGMII mode.
Specifically, all three loopback modes, transceiver, port swap, and all repeater modes operate properly.
PARALLEL INTERFACE MODES
The TLK2226 provides an RTBI compliant interface or an RGMII compliant interface. Each parallel channel
provides 5 bit busses clocked in Double Data Rate (DDR) fashion. The five least significant bits of data are
latched on the rising edge of the transmit clock are put together with the 5 most significant bits of data latched
on the falling edge of the clock.
The parallel transmit busses may be configured such that a single transmit clock (TCLKC) is used to clock in the
parallel data for all 6 channels, or each parallel transmit bus may have its own transmit clock. The transmit
clocks must not have any frequency deviation relative to REFCLK. Each transmit channel employs a small FIFO
to allow for arbitrary phase relationships between the transmit clock and REFCLK, but the transmit FIFO will not
account for frequency variance between the transmit clocks and REFCLK. On the receive side, if the CTC FIFO
is used for a given channel, then the receive data bus for that channel will be clocked out by a buffered version
of REFCLK. If the CTC FIFO is not used, then the recovered byte clock for that channel will be 1/10th the rate of
the incoming serial data stream.
The interface modes can be controlled via CODE and CTC. A summary of the TLK2226 parallel interface modes
is shown in Table 2.
Low
High
CODE
Low=RTBI
High=RGMII
RTBI Mode
Bit[4] Data[4]
Bit[3] Data[3]
Bit[2] Data[2]
Bit[1] Data[1]
Bit[0] Data[0]
CLK ↑
Data[9]
Data[8]
Data[7]
Data[6]
Data[5]
↑
RGMII Mode
Bit[4] CTRL1
Bit[3] Data[3]
Bit[2] Data[2]
Bit[1] Data[1]
Bit[0] Data[0]
CLK ↑
CTRL2
Data[7]
Data[6]
Data[5]
Data[4]
↑
Table 2. Parallel Interface Modes
CTC
Low=disable
High=enable
x
DESCRIPTION
RTBI channel mode:
• No clock tolerance compensation is performed on Receive data.
• Data towards MAC are aligned to individual RCLKs on a
source-centered/aligned mode per channel basis
Low
High
RGMII (without CTC) channel mode:
• No clock tolerance compensation is performed
• Data towards MAC are aligned to individual RCLKs on a
source-centered/aligned per channel basis.
RGMII channel mode
• All data towards MAC are aligned to RCLKx thru CTC FIFO. (TLK2226
• accepts +/-200ppm frequency offset on the receive data relative to the
transmit data.)
Each RCLKx is a buffered version of REFCLK, source centered/aligned
relative to the receive data.
TRANSMIT DATA PATH
The transmit logic converts parallel data into an NRZ serial bit stream with a differential VML output at a rate of
from 1.0 to 1.3Gbps
Transmit Clock Interface
Transmit clocks for all channels is expected to be the same frequency as the reference clock, REFCLK, but of
arbitrary phase relationship to REFCLK.
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