TLK2226_09 Datasheet, PDF (15/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

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TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
DETAILED DESCRIPTION
REFERENCE CLOCK SYNTHESIZER (PLL)
The TLK2226 employs a mature Phase Lock Loop (PLL) design in use for Gigabit Ethernet transceivers and
high-speed serial links by Texas Instruments since 1997 on both standard products and custom ASIC designs.
This PLL design is used to synthesize the serial line rate bit clock from the REFCLK input as well as generate
clocks for the receiver sampling circuitry. The PLL and associated high speed circuitry is powered by the analog
power supply pins (VDDA) with isolated grounds (GNDA). Care should be taken in providing a low noise
environment in a system. It is recommended to supply the VDDA reference by separate isolated plane within the
system printed circuit board (PCB). It is recommended that systems employing switching power supplies provide
proper filtering of the fundamental and harmonic components in the 1MHz-10Mhz band to avoid bit errors from
injected noise. It is strongly recommended that no PLL based clock synthesizer circuit be used as the source for
the REFCLK. This could cause accumulation of jitter between the two PLL's
OPERATING MODES
The TLK2226 has two operational modes with respect to the Physical Coding Sublayer (PCS) functions called
RTBI mode and RGMII mode. The RTBI or RGMII mode is selectable via the CODE bit in MDIO register space
or the CODE pin as described in Table 1. The CODE pin is gated with the internal CODE register such that
setting the pin to a logic zero disables the PCS functions, setting the CODE pin to a logic one enables PCS
functions and permits these functions to be disabled on a channel by channel basis via MDIO control. In
addition, all PCS functions except the CTC FIFO may be enabled if the CTC FIFO is to be implemented in the
protocol device. The CTC FIFO may be disabled by way of the CTC_EN pin or the CTC_EN bit in the MDIO
register space. Besides the RTBI or RGMII modes, additional modes of operation include the serial repeater
mode with CTC FIFO mode, serial repeater without CTC FIFO mode, RGMII port swap mode, and 1/10 rate for
100FX mode.
CODE
Low
High
Table 1. PCS Operational Modes
OPERATING MODES
RTBI mode. Disables PCS functions for each channel. Refer to Byte Alignment Logic section, for additional description over
this mode.
RGMII mode. Enables PCS functions for each channel. Data on the transmit and receive data bus is treated as un-coded
data.
RTBI MODE
In RTBI mode, the transmit data bus for each channel accepts 5-bit wide encoded data on the transmit data bus
pins. Data is latched on the rising and falling edge of the transmit data clock. The encoded data is then
phase-aligned, serialized and transmitted sequentially beginning with bit 0 over the differential high speed serial
transmit pins. The receive data bus for each channel outputs 5-bit wide data. Data is output relative to both the
rising and falling edge of the receive clock.
RX RTBI A
TX RTBI A
TX RTBI B
RX RTBI B
5bit DDR
to
10bit
SDR
Interface
5bit DDR
to
10bit
SDR
Interface
PCS
Logic
PCS
Logic
CTC
Decode
Encode
Encode
Decode
CTC
channel A
TX Analog
Core
channel B
2 of the 6 channels of TLK2226 shown
data path for RTBI mode
Figure 14. RTBI Mode Block Diagram
RX Analog
Core
channel A
channel B
+
TXA_{_}
+
_^RXA
+
RXB
_
+
TXB_{_}
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