MSP430FR5729 Datasheet, PDF (75/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
7.4 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
00
01
From module 2
10
11
P2OUT.x
From module 1
From module 2
From module 3
P2SEL0.x
P2SEL1.x
P2IN.x
To modules
00
01
10
11
EN
D
DVSS
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
Bus
Keeper
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
Table 7-4. Port P2 (P2.0 to P2.2) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
0 P2.0 (I/O)
TB2.CCI0A ⁽¹⁾
TB2.0 ⁽¹⁾
UCA0TXD/UCA0SIMO
TB0CLK
ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
1 P2.1 (I/O)
TB2.CCI1A ⁽¹⁾
TB2.1 ⁽¹⁾
UCA0RXD/UCA0SOMI
TB0.CCI0A
TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
2 P2.2 (I/O)
TB2.CCI2A ⁽¹⁾
TB2.2 ⁽¹⁾
UCB0CLK
TB1.CCI0A ⁽¹⁾
TB1.0 ⁽¹⁾
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B0 module.
CONTROL BITS/SIGNALS
P2DIR.x P2SEL1.x P2SEL0.x
I: 0; O: 1
0
0
0
0
1
1
X ⁽²⁾
1
0
0
1
1
1
I: 0; O: 1
0
0
0
0
1
1
X ⁽²⁾
1
0
0
1
1
1
I: 0; O: 1
0
0
0
0
1
1
X ⁽³⁾
1
0
0
1
1
1
Copyright © 2014, Texas Instruments Incorporated
Input/Output Schematics
75
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Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720