MSP430FR5729 Datasheet, PDF (5/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
3 Device Comparison
Table 3-1 summarizes the available family members.
Device
MSP430FR5729
MSP430FR5728
MSP430FR5727
MSP430FR5726
MSP430FR5725
MSP430FR5724
MSP430FR5723
MSP430FR5722
MSP430FR5721
MSP430FR5720
Table 3-1. Family Members⁽¹⁾⁽²⁾
FRAM
(KB)
SRAM
(KB)
System
Clock
(MHz)
ADC10_B
eUSCI
Comp_D
Timer_A ⁽³⁾
Timer_B ⁽⁴⁾
Channel A:
UART, IrDA,
SPI
Channel B:
SPI, I²C
I/O
16
1
8
12 ext, 2 int ch.
16 ch.
3, 3
3, 3, 3
2
32
1
30
6 ext, 2 int ch.
10 ch.
17
16
1
8
3, 3
3
1
1
8 ext, 2 int ch.
12 ch.
21
16
1
8
32
-
16 ch.
3, 3
3, 3, 3
2
1
30
16
1
8
10 ch.
17
-
3, 3
3
1
1
12 ch.
21
8
1
8
12 ext, 2 int ch.
16 ch.
3, 3
3, 3, 3
2
32
1
30
6 ext, 2 int ch.
10 ch.
17
8
1
8
3, 3
3
1
1
8 ext, 2 int ch.
12 ch.
21
8
1
8
32
-
16 ch.
3, 3
3, 3, 3
2
1
30
8
1
8
10 ch.
17
-
3, 3
3
1
1
12 ch.
21
4
1
8
12 ext, 2 int ch.
16 ch.
3, 3
3, 3, 3
2
32
1
30
6 ext, 2 int ch.
10 ch.
17
4
1
8
3, 3
3
1
1
8 ext, 2 int ch.
12 ch.
21
Package
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
(1) For the most current package and ordering information, see the Package Option Addendum in Section 10, or see the TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
Device Comparison
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