MSP430FR5729 Datasheet, PDF (26/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
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5.20 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_TA
Timer_A input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
V_CC
2 V, 3 V
MIN TYP
t_TA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
2 V, 3 V
20
MAX UNIT
8 MHz
ns
5.21 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_TB
Timer_B input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
V_CC
2 V, 3 V
MIN TYP
t_TB,cap
Timer_B capture timing
All capture inputs, Minimum pulse
duration required for capture
2 V, 3 V
20
MAX UNIT
8 MHz
ns
5.22 eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
MIN TYP MAX UNIT
f_SYSTEM MHz
5 MHz
5.23 eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
V_CC
MIN TYP MAX UNIT
5
15
20
t_t UART receive deglitch time⁽¹⁾
UCGLITx = 1
UCGLITx = 2
2 V, 3 V
20
45
60
ns
35
80
120
UCGLITx = 3
50 110
180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
26
Specifications
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