MSP430FR5729 Datasheet, PDF (13/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
NAME
Table 4-1. Signal Descriptions (continued)
TERMINAL
RHA
NO.
RGE DA
I/O ⁽¹⁾
PW
DESCRIPTION
P2.4/TA1.0/UCA1CLK/
A7/CD11
AVSS
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options RGE)
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on package options
RGE)
35 N/A 37 28 I/O
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1
SPI master mode (not available on devices without eUSCI_A1)
Analog input A7 – ADC (not available on devices without ADC)
36 N/A 38 N/A
Comparator_D input CD11 (not available on package options RGE)
Analog ground supply
PJ.4/XIN
37 21
1
1
I/O ^{General-purpose digital I/O}
Input terminal for crystal oscillator XT1
PJ.5/XOUT
AVSS
AVCC
QFN Pad
38 22
2
2
I/O ^{General-purpose digital I/O}
Output terminal of crystal oscillator XT1
39 23
3
3
Analog ground supply
40 24
4
4
Analog power supply
Pad Pad N/A N/A
QFN package pad. Connection to VSS recommended.
Copyright © 2014, Texas Instruments Incorporated
Terminal Configuration and Functions
13
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