MSP430FR5729 Datasheet, PDF (15/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
5.4 Active Mode Supply Current Into V_CC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)^{(1) (2) (3)}
PARAMETER
EXECUTION MEMORY
V_CC
1 MHz
TYP
MAX
Frequency (f_MCLK = f_SMCLK)
4 MHz
TYP
MAX
8 MHz
TYP
MAX
UNIT
I_AM,
(4)
FRAM_UNI
I_AM,0% ⁽⁵⁾
FRAM
3V
FRAM
0% cache hit ratio
3V
0.27
0.58
1.0
mA
0.42
0.73
1.2
1.6
2.2
2.8
I_AM,50% ^{(5) (6)}
FRAM
50% cache hit ratio
3V
0.31
0.73
1.3
I_AM,66% ^{(5) (6)}
FRAM
66% cache hit ratio
3V
0.27
0.58
1.0
mA
I_AM,75% ^{(5) (6)}
FRAM
75% cache hit ratio
3V
0.25
0.5
0.82
I_AM,100% ^{(5) (6)}
I_AM,
(6)
RAM
(7)
FRAM
100% cache hit ratio
3V
RAM
3V
0.2
0.43
0.3
0.55
0.42
0.8
0.2
0.4
0.35
0.55
0.55
0.75 mA
(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Characterized with program executing typical data processing.
(4) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.
(5) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
(6) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in .
f_ACLK = 32786 Hz, f_MCLK = f_SMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(7) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.
Typical Active Mode Supply Current, No Wait States
2.50
2.00
IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724
IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669
1.50
IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646
IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708
1.00
0.50
IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150
IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708
0.00
0
1
2
3
4
5
6
7
8
9
fMCLK = fSMCLK, MHz
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
Copyright © 2014, Texas Instruments Incorporated
Specifications
15
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