MSP430FR5729 Datasheet, PDF (2/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
www.ti.com
1.3 Description
The Texas Instruments MSP430FR572x family of ultra-low-power microcontrollers consists of multiple
devices that feature embedded FRAM nonvolatile memory, ultra-low-power 16-bit MSP430™ CPU, and
different peripherals targeted for various applications. The architecture, FRAM, and peripherals, combined
with seven low-power modes, are optimized to achieve extended battery life in portable and wireless
sensing applications. FRAM is a new nonvolatile memory that combines the speed, flexibility, and
endurance of SRAM with the stability and reliability of flash, all at lower total power consumption.
Peripherals include a 10-bit ADC, a 16-channel comparator with voltage reference generation and
hysteresis capabilities, three enhanced serial channels capable of I²C, SPI, or UART protocols, an internal
DMA, a hardware multiplier, an RTC, five 16-bit timers, and digital I/Os.
PART NUMBER
Device Information⁽¹⁾
PACKAGE
BODY SIZE⁽²⁾
MSP430FR5729RHA
VQFN (40)
6 mm x 6 mm
MSP430FR5729DA
TSSOP (38)
12.5 mm x 6.2 mm
MSP430FR5728RGE
VQFN (24)
4 mm x 4 mm
MSP430FR5728PW
TSSOP (28)
9.7 mm x 4.4 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 10, or see the TI web site
at www.ti.com.
(2) The dimensions shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 10.
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and
MSP430FR5729 devices in the RHA package. For the functional block diagrams for all device variants
and package options, see Section 6.1.
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
PA
PB
P1.x P2.x P3.x P4.x
Clock
System
ACLK
SMCLK
16 KB
(FR5729)
8 KB
(FR5725)
4 KB
(FR5721)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
TB1
TB2
(2) Timer_A (3) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 Bit
200KSPS
Comp_D
16 channels
14 channels
(12 ext/2 int)
Figure 1-1. Functional Block Diagram – RHA Package – MSP430FR5721, MSP430FR5725, MSP430FR5729
2
Device Overview
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Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720