MSP430FR5729 Datasheet, PDF (11/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

www.ti.com
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
NAME
Table 4-1. Signal Descriptions (continued)
TERMINAL
RHA
NO.
RGE DA
I/O ⁽¹⁾
PW
DESCRIPTION
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
General-purpose digital I/O with port interrupt and wake up from LPMx.5
17 N/A 19 15 I/O TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI
mode (not available on devices without UCSI_A1)
P2.6/TB1.0/UCA1RXD/
UCA1SOMI
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without
18 N/A 20
16
I/O _TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode
(not available on devices without UCSI_A1)
TEST/SBWTCK ^{(2) (3)}
19 11 21 17
I ^{Test mode pin – enable JTAG pins}
Spy-Bi-Wire input clock
RST/NMI/SBWTDIO ^{(2) (3)}
Reset input active low
20
12
22
18
I/O _{Non-maskable interrupt input}
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without
TB2)
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK ⁽⁴⁾
21
13
23
19 I/O Transmit data – eUSCI_A0 UART mode
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0 ⁽⁴⁾
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without
TB2)
22 14 24 20 I/O
Receive data – eUSCI_A0 UART mode
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.2/TB2.2/UCB0CLK/ TB1.0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without
TB2)
23 15 25 21 I/O
Clock
signal
input
–
eUSCI_B0
SPI
slave
mode,
Clock signal output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without
TB1)
P3.4/TB1.1/TB2CLK/ SMCLK
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
24
N/A
26
N/A
I/O
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without
TB1)
TB2 clock input (not available on devices without TB2 or package options PW, RGE)
SMCLK output (not available on package options PW, RGE)
(3) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions.
(4) See Section 6.6 and Section 6.7 for use with BSL and JTAG functions.
Copyright © 2014, Texas Instruments Incorporated
Terminal Configuration and Functions
11
Submit Documentation Feedback
Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720