MSP430FR5729 Datasheet, PDF (41/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
6.1.5 Functional Block Diagram – MSP430FR5720IRGE, MSP430FR5724IRGE,
MSP430FR5728IRGE
Figure 6-5 shows the functional block diagram for the MSP430FR5720, MSP430FR5724, and
MSP430FR5728 devices in the RGE package.
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
PA
P1.x P2.x
Clock
System
ACLK
SMCLK
16 KB
(FR5728)
8 KB
(FR5724)
4 KB
(FR5720)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
Interrupt
& Wakeup
PA
1×11 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
(2) Timer_A (1) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
ADC10_B
10 Bit
200KSPS
8 channels
(6 ext/2 int)
Comp_D
10 channels
Figure 6-5. Functional Block Diagram – RGE Package – MSP430FR5720, MSP430FR5724, MSP430FR5728
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
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MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720