MSP430FR5729 Datasheet, PDF (47/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
Table 6-1. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
eUSCI_A1 Receive and Transmit
DMA
TA1
TA1
I/O Port P1
TB1
TB1
I/O Port P2
TB2
TB2
I/O Port P3
I/O Port P4
RTC_B
INTERRUPT FLAG
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
(UCA1IV) ^{(1) (3)}
DMA0IFG, DMA1IFG, DMA2IFG
(DMAIV) ^{(1) (3)}
TA1CCR0 CCIFG0 ⁽³⁾
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
(TA1IV) ^{(1) (3)}
P1IFG.0 to P1IFG.7
(P1IV) ^{(1) (3)}
TB1CCR0 CCIFG0 ⁽³⁾
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
(TB1IV) ^{(1) (3)}
P2IFG.0 to P2IFG.7
(P2IV) ^{(1) (3)}
TB2CCR0 CCIFG0 ⁽³⁾
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
(TB2IV) ^{(1) (3)}
P3IFG.0 to P3IFG.7
(P3IV) ^{(5) (6)}
P4IFG.0 to P4IFG.2
(P4IV) ^{(5) (6)}
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) ^{(5) (6)}
Reserved
Reserved ⁽⁷⁾
SYSTEM
INTERRUPT
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
PRIORITY
0FFE6h
51
0FFE4h
0FFE2h
0FFE0h
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
0FFD4h
0FFD2h
0FFD0h
0FFCEh
0FFCCh
⋮
0FF80h
50
49
48
47
46
45
44
43
42
41
40
39
38
⋮
0, lowest
(5) Multiple source flags
(6) Interrupt flags are located in the module.
(7) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
47
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