MSP430FR5729 Datasheet, PDF (74/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
7.3 Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
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P1REN.x
P1DIR.x
00
01
From module 2
10
11
P1OUT.x
From module 1
From module 2
From module 3
P1SEL0.x
P1SEL1.x
P1IN.x
To modules
00
01
10
11
EN
D
DVSS
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
Bus
Keeper
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
Table 7-3. Port P1 (P1.6 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
6
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
7
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_B0 module.
P1.6 (I/O)
TB1.CCI1A ⁽¹⁾
TB1.1 ⁽¹⁾
UCB0SIMO/UCB0SDA
TA0.CCI0A
TA0.0
P1.7 (I/O)
TB1.CCI2A ⁽¹⁾
TB1.2 ⁽¹⁾
UCB0SOMI/UCB0SCL
TA1.CCI0A
TA1.0
CONTROL BITS/SIGNALS
P1DIR.x P1SEL1.x P1SEL0.x
I: 0; O: 1
0
0
0
0
1
1
X ⁽²⁾
1
0
0
1
1
1
I: 0; O: 1
0
0
0
0
1
1
X ⁽²⁾
1
0
0
1
1
1
74
Input/Output Schematics
Copyright © 2014, Texas Instruments Incorporated
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MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720