MSP430FR5729 Datasheet, PDF (27/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
5.24 eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_eUSCI eUSCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
5.25 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE active to clock
TEST CONDITIONS
UCSTEM = 0,
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
V_CC
2 V, 3 V
2 V, 3 V
MIN TYP MAX UNIT
1
UCxCLK
cycles
1
t_STE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 0,
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
1
2 V, 3 V
1
UCxCLK
cycles
t_STE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 0,
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
2 V, 3 V
55
ns
35
t_STE,DIS
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 0,
UCMODEx = 01 or 10
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
2 V, 3 V
40
ns
30
t_SU,MI
SOMI input data setup time
2V
35
ns
3V
35
t_HD,MI
SOMI input data hold time
2V
0
ns
3V
0
t_VALID,MO SIMO output data valid time ⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2V
3V
30
ns
30
t_HD,MO
SIMO output data hold time ⁽³⁾
C_L = 20 pF
2V
0
ns
3V
0
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-6 and Figure 5-7.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-
6 and Figure 5-7.
Copyright © 2014, Texas Instruments Incorporated
Specifications
27
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