MSP430FR5729 Datasheet, PDF (12/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
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SLASE35A – MAY 2014 – REVISED JUNE 2014
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NAME
Table 4-1. Signal Descriptions (continued)
TERMINAL
RHA
NO.
RGE DA
I/O ⁽¹⁾
PW
DESCRIPTION
P3.5/TB1.2/CDOUT
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
25 N/A 27 N/A I/O _{TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without}
TB1)
Comparator_D output (not available on package options PW, RGE)
P3.6/TB2.1/TB1CLK
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
26 N/A 28 N/A I/O _{TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without}
TB2)
TB1 clock input (not available on devices without TB1 or package options PW, RGE)
P3.7/TB2.2
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
27 N/A 29 N/A I/O ^{available on package options PW, RGE)}
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without
TB2 or package options PW, RGE)
P1.6/TB1.1/UCB0SIMO/
UCB0SDA/TA0.0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without
TB1)
28 16 30 22 I/O
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
P1.7/TB1.2/UCB0SOMI/
UCB0SCL/TA1.0
VCORE ⁽⁵⁾
DVSS
DVCC
P2.7
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without
TB1)
29 17 31 23 I/O
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
30 18 32 24
Regulated core power supply (internal use only, no external current loading)
31 19 33 25
Digital ground supply
32 20 34 26
Digital power supply
33
N/A
35
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
P2.3/TA0.0/UCA1STE/
A6/CD10
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options RGE)
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on package options
RGE)
34 N/A 36 27 I/O
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without
eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE)
(5) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C_VCORE.
12
Terminal Configuration and Functions
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