MSP430FR5729 Datasheet, PDF (45/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
6.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3 Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An
interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request,
and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5
and LPM4.5 disable the core supply to minimize power consumption.
The following eight operating modes can be configured by software:
• Active mode (AM)
• Low-power mode 3 (LPM3)
– All clocks are active
– CPU is disabled
• Low-power mode 0 (LPM0)
– ACLK active
– CPU is disabled
– MCLK and SMCLK disabled
– ACLK active
– DCO disabled
– MCLK disabled
– Complete data retention
– SMCLK optionally active
• Low-power mode 4 (LPM4)
– Complete data retention
– CPU is disabled
• Low-power mode 1 (LPM1)
– ACLK, MCLK, SMCLK disabled
– CPU is disabled
– Complete data retention
– ACLK active
• Low-power mode 3.5 (LPM3.5)
– MCLK disabled
– RTC operation
– SMCLK optionally active
– Internal regulator disabled
– DCO disabled
– No data retention
– Complete data retention
– I/O pad state retention
• Low-power mode 2 (LPM2)
– CPU is disabled
– ACLK active
– MCLK disabled
– SMCLK optionally active
– DCO disabled
– Complete data retention
– Wakeup from RST, general-purpose
I/O, RTC events
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– I/O pad state retention
– Wakeup from RST and general-purpose
I/O
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
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