MSP430FR5729 Datasheet, PDF (7/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
4.2 Pin Diagram – DA Package –
MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
Figure 4-2 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725,
MSP430FR5727, and MSP430FR5729 devices in the 38-pin DA package.
DA PACKAGE
(TOP VIEW)
PJ.4/XIN 1
PJ.5/XOUT 2
AVSS 3
AVCC
4
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-* 5
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+* ⁶
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2 7
P3.0/A12*/CD12 ⁸
P3.1/A13*/CD13 ⁹
P3.2/A14*/CD14 ¹⁰
P3.3/A15*/CD15 ¹¹
P1.3/TA1.2/UCB0STE/A3*/CD3 12
P1.4/TB0.1/UCA0STE/A4*/CD4 13
P1.5/TB0.2/UCA0CLK/A5*/CD5 14
PJ.0/TDO/TB0OUTH/SMCLK/CD6 15
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
16
PJ.2/TMS/TB2OUTH/ACLK/CD8 17
PJ.3/TCK/CD9 18
P2.5/TB0.0/UCA1TXD/UCA1SIMO 19
38 AVSS
37 P2.4/TA1.0/UCA1CLK/A7*/CD11
36 P2.3/TA0.0/UCA1STE/A6*/CD10
35 _P2.7
34 DVCC
33 DVSS
32 VCORE
31 P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
30 P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
29 _P3.7/TB2.2
28 _{P3.6/TB2.1/TB1CLK}
27 _{P3.5/TB1.2/CDOUT}
26 _{P3.4/TB1.1/TB2CLK/SMCLK}
25 P2.2/TB2.2/UCB0CLK/TB1.0
24 P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
23 P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
22 _{RST/NMI/SBWTDIO}
21 TEST/SBWTCK
20 P2.6/TB1.0/UCA1RXD/UCA1SOMI
* Not available on MSP430FR5727, MSP430FR5723
Figure 4-2. 38-Pin DA Package (Top View)
4.3 Pin Diagram – RGE Package –
MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
Figure 4-3 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724,
MSP430FR5726, and MSP430FR5728 devices in the 24-pin RGE package.
PJ.5/XOUT
AVSS
AVCC
RGE PACKAGE
(TOP VIEW)
PJ.4/XIN
DVCC
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-* 1
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+* 2
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2 3
P1.3/TA1.2/UCB0STE/A3*/CD3 4
P1.4/TB0.1/UCA0STE/A4*/CD4 5
P1.5/TB0.2/UCA0CLK/A5*/CD5 6
18 _VCORE
17 P1.7/UCB0SOMI/UCB0SCL/TA1.0
16 P1.6/UCB0SIMO/UCB0SDA/TA0.0
15 _P2.2/UCB0CLK
14 P2.1/UCA0RXD/UCA0SOMI/TB0.0
13 P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
Note:
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
* Not available on MSP430FR5726, MSP430FR5722
Exposed thermal pad connection to V_SS recommended.
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK/CD9
Figure 4-3. 24-Pin RGE Package (Top View)
Copyright © 2014, Texas Instruments Incorporated
Terminal Configuration and Functions
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Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720