MSP430FR5729 Datasheet, PDF (31/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
5.27 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-10)
f_eUSCI
PARAMETER
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_SCL
t_HD,STA
t_SU,STA
t_HD,DAT
t_SU,DAT
t_SU,STO
SCL clock frequency
Hold time (repeated) START
Setup time for a repeated START
Data hold time
Data setup time
Setup time for STOP
f_SCL = 100 kHz
f_SCL > 100 kHz
f_SCL = 100 kHz
f_SCL > 100 kHz
f_SCL = 100 kHz
f_SCL > 100 kHz
UCGLITx = 0
2 V, 3 V
0
4.0
2 V, 3 V
0.6
4.7
2 V, 3 V
0.6
2 V, 3 V
0
2 V, 3 V
250
4.0
2 V, 3 V
0.6
50
400 kHz
µs
µs
ns
ns
µs
600 ns
t_SP
Pulse duration of spikes suppressed by
input filter
UCGLITx = 1
UCGLITx = 2
25
2 V, 3 V
12.5
300 ns
150 ns
UCGLITx = 3
6.25
75 ns
UCCLTOx = 1
27
ms
t_TIMEOUT Clock low timeout
UCCLTOx = 2
UCCLTOx = 3
2 V, 3 V
30
ms
33
ms
SDA
t_HD,STA
t_SU,STA
t_HD,STA
t_BUF
t_LOW
t_HIGH
t_SP
SCL
t_HD,DAT
t_SU,DAT
Figure 5-10. I2C Mode Timing
t_SU,STO
Copyright © 2014, Texas Instruments Incorporated
Specifications
31
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