MSP430FR5729 Datasheet, PDF (46/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
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6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-Up, Brownout, Supply
Supervisors
External Reset RST
Watchdog Timeout (Watchdog
mode)
WDT, FRCTL MPU, CS, PMM
Password Violation
FRAM double bit error detection
MPU segment violation
Software POR, BOR
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
FRAM single, double bit error
detection
User NMI
External NMI
Oscillator Fault
Comparator_D
TB0
TB0
Watchdog Timer
(Interval Timer Mode)
eUSCI_A0 Receive and Transmit
eUSCI_B0 Receive and Transmit
ADC10_B
TA0
TA0
SVSLIFG, SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) ^{(1) (2)}
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
SBDIFG, DBDIFG
(SYSSNIV) ⁽¹⁾
NMIIFG, OFIFG
(SYSUNIV) ^{(1) (2)}
Comparator_D interrupt flags
(CBIV) ^{(1) (3)}
TB0CCR0 CCIFG0 ⁽³⁾
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
(TB0IV) ^{(1) (3)}
WDTIFG
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
(UCA0IV) ^{(1) (3)}
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(UCB0IV) ^{(1) (3)}
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(ADC10IV) ^{(1) (3) (4)}
TA0CCR0 CCIFG0 ⁽³⁾
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(TA0IV) ^{(1) (3)}
SYSTEM
INTERRUPT
Reset
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
PRIORITY
0FFFEh
63, highest
0FFFCh
62
0FFFAh
61
0FFF8h
60
0FFF6h
59
0FFF4h
58
0FFF2h
57
0FFF0h
56
0FFEEh
55
0FFECh
54
0FFEAh
53
0FFE8h
52
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
46
Detailed Description
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