MSP430FR5729 Datasheet, PDF (3/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 2
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 4
3 Device Comparison ..................................... 5
4 Terminal Configuration and Functions.............. 6
4.1 Pin Diagram – RHA Package –
MSP430FR5721, MSP430FR5723,
MSP430FR5725, MSP430FR5727, MSP430FR5729 6
4.2 Pin Diagram – DA Package –
MSP430FR5721, MSP430FR5723,
MSP430FR5725, MSP430FR5727, MSP430FR5729 7
4.3 Pin Diagram – RGE Package –
MSP430FR5720, MSP430FR5722,
MSP430FR5724, MSP430FR5726, MSP430FR5728 7
4.4 Pin Diagram – PW Package –
MSP430FR5720, MSP430FR5722,
MSP430FR5724, MSP430FR5726, MSP430FR5728 8
4.5 Signal Descriptions ................................... 9
5 Specifications ........................................... 14
5.1 Absolute Maximum Ratings ........................ 14
5.2 Handling Ratings .................................... 14
5.3 Recommended Operating Conditions............... 14
5.4 Active Mode Supply Current Into V_CC Excluding
External Current..................................... 15
5.5 LEoxwcl-uPdoinwgerEMxteordneaSl _{CupuprrleynCt.}u_.r_.r_.e_.n_.t_.s_..(_.I_.n_.t_.o_..V_.C.C..)_{....... 16}
5.6 Schmitt-Trigger Inputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI)....................... 17
5.7 Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7) ........................ 17
5.8 Leakage Current – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI)....................... 17
5.9 Outputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) ................................. 18
5.10 Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) ................................. 18
5.11 Typical Characteristics – Outputs ................... 19
5.12 Crystal Oscillator, XT1, Low-Frequency (LF) Mode 21
5.13 Crystal Oscillator, XT1, High-Frequency (HF) Mode
...................................................... 22
5.14 Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 23
5.15 DCO Frequencies ................................... 24
5.16 MODOSC............................................ 24
5.17 PMM, Core Voltage ................................. 25
5.18 PMM, SVS, BOR.................................... 25
5.19 Wake-Up from Low Power Modes .................. 25
5.20 Timer_A ............................................. 26
5.21 Timer_B ............................................. 26
5.22 eUSCI (UART Mode) Recommended Operating
Conditions ........................................... 26
5.23 eUSCI (UART Mode)................................ 26
5.24 eUSCI (SPI Master Mode) Recommended
Operating Conditions................................ 27
5.25 eUSCI (SPI Master Mode) .......................... 27
5.26 eUSCI (SPI Slave Mode) ........................... 29
5.27 eUSCI (I2C Mode) .................................. 31
5.28 10-Bit ADC, Power Supply and Input Range
Conditions ........................................... 32
5.29 10-Bit ADC, Timing Parameters .................... 32
5.30 10-Bit ADC, Linearity Parameters .................. 32
5.31 REF, External Reference ........................... 33
5.32 REF, Built-In Reference............................. 33
5.33 REF, Temperature Sensor and Built-In V_MID ....... 34
5.34 Comparator_D....................................... 35
5.35 FRAM................................................ 35
5.36 JTAG and Spy-Bi-Wire Interface.................... 36
6 Detailed Description ................................... 37
6.1 Functional Block Diagrams.......................... 37
6.2 CPU ................................................. 45
6.3 Operating Modes.................................... 45
6.4 Interrupt Vector Addresses.......................... 46
6.5 Memory Organization ............................... 48
6.6 Bootstrap Loader (BSL) ............................. 49
6.7 JTAG Operation ..................................... 49
6.8 FRAM ............................................... 50
6.9 Memory Protection Unit (MPU) ..................... 50
6.10 Peripherals .......................................... 50
7 Input/Output Schematics ............................ 70
7.1 Port P1, P1.0 to P1.2, Input/Output With Schmitt
Trigger............................................... 70
7.2 Port P1, P1.3 to P1.5, Input/Output With Schmitt
Trigger............................................... 72
7.3 Port P1, P1.6 to P1.7, Input/Output With Schmitt
Trigger............................................... 74
7.4 Port P2, P2.0 to P2.2, Input/Output With Schmitt
Trigger............................................... 75
7.5 Port P2, P2.3 to P2.4, Input/Output With Schmitt
Trigger............................................... 76
7.6 Port P2, P2.5 to P2.6, Input/Output With Schmitt
Trigger............................................... 78
7.7 Port P2, P2.7, Input/Output With Schmitt Trigger... 79
7.8 Port P3, P3.0 to P3.3, Input/Output With Schmitt
Trigger............................................... 80
7.9 Port P3, P3.4 to P3.6, Input/Output With Schmitt
Trigger............................................... 82
7.10 Port P3, P3.7, Input/Output With Schmitt Trigger... 83
7.11 Port P4, P4.0, Input/Output With Schmitt Trigger... 84
7.12 Port P4, P4.1, Input/Output With Schmitt Trigger... 85
7.13 Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK,
TDI/TCLK, Input/Output With Schmitt Trigger or
Output ............................................... 86
7.14 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt
Trigger............................................... 89
8 Device Descriptors (TLV) ............................. 91
Copyright © 2014, Texas Instruments Incorporated
Table of Contents
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MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720