MSP430FR5729 Datasheet, PDF (10/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
www.ti.com
NAME
Table 4-1. Signal Descriptions (continued)
TERMINAL
RHA
NO.
RGE DA
I/O ⁽¹⁾
PW
DESCRIPTION
P1.3/TA1.2/UCB0STE/ A3/CD3 8
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
4
12
8
I/O _{Slave transmit enable – eUSCI_B0 SPI mode}
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
P1.4/TB0.1/UCA0STE/ A4/CD4 9
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
5
13
9
I/O _{Slave transmit enable – eUSCI_A0 SPI mode}
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/ A5/CD5 10
6
14
10 I/O Clock
signal
input
–
eUSCI_A0
SPI
slave
mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
PJ.0/TDO/TB0OUTH/
SMCLK/CD6 ⁽²⁾
General-purpose digital I/O
Test data output port
11
7
15
11
I/O _{Switch all PWM outputs high impedance input – TB0}
SMCLK output
Comparator_D input CD6
PJ.1/TDI/TCLK/TB1OUTH/
MCLK/CD7 ⁽²⁾
General-purpose digital I/O
Test data input or test clock input
12
8
16 12 I/O Switch all PWM outputs high impedance input – TB1 (not available on devices
without TB1)
MCLK output
Comparator_D input CD7
PJ.2/TMS/TB2OUTH/
ACLK/CD8 ⁽²⁾
General-purpose digital I/O
Test mode select
13
9
17 13 I/O Switch all PWM outputs high impedance input – TB2 (not available on devices
without TB2)
ACLK output
Comparator_D input CD8
PJ.3/TCK/CD9 ⁽²⁾
General-purpose digital I/O
14
10
18
14
I/O _{Test clock}
Comparator_D input CD9
P4.0/TB2.0
P4.1
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
15 N/A N/A N/A I/O ^{available on package options PW, RGE)}
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without
TB2 or package options DA, PW, RGE)
16
N/A N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options DA, PW, RGE)
(2) See Section 6.7 for use with JTAG function.
10
Terminal Configuration and Functions
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720