MSP430FR5729 Datasheet, PDF (29/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
5.26 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾
PARAMETER
t_STE,LEAD STE lead time, STE active to clock
TEST CONDITIONS
V_CC
MIN TYP MAX UNIT
2V
7
ns
3V
7
t_STE,LAG STE lag time, Last clock to STE inactive
2V
0
ns
3V
0
t_STE,ACC STE access time, STE active to SOMI data out
2V
65
ns
3V
40
t_STE,DIS
STE disable time, STE inactive to SOMI high
impedance
2V
40
ns
3V
35
t_SU,SI
SIMO input data setup time
2V
2
ns
3V
2
t_HD,SI
SIMO input data hold time
2V
5
ns
3V
5
t_VALID,SO SOMI output data valid time ⁽²⁾
UCLK edge to SOMI valid,
2V
C_L = 20 pF
3V
30
ns
30
t_HD,SO
SOMI output data hold time ⁽³⁾
C_L = 20 pF
2V
4
ns
3V
4
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-8 and Figure 5-9.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8
and Figure 5-9.
Copyright © 2014, Texas Instruments Incorporated
Specifications
29
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