MSP430FR5729 Datasheet, PDF (61/115 Pages) Texas Instruments – MSP430FR572x Mixed-Signal Microcontrollers

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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
SLASE35A – MAY 2014 – REVISED JUNE 2014
Table 6-20. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
System control
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
REGISTER
SYSCTL
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
OFFSET
00h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Table 6-21. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
00h
OFFSET
Table 6-22. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
Port P1 input
Port P1 output
Port P1 direction
Port P1 pullup/pulldown enable
Port P1 selection 0
Port P1 selection 1
Port P1 interrupt vector word
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
REGISTER
P1IN
P1OUT
P1DIR
P1REN
P1SEL0
P1SEL1
P1IV
P1SELC
P1IES
P1IE
P1IFG
P2IN
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
P2IES
P2IE
P2IFG
OFFSET
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
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MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720