C8051F980-C-GM Datasheet, PDF (93/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
7. Comparator
C8051F99x-C8051F98x devices include an on-chip programmable voltage comparator: Comparator 0
(CPT0) shown in Figure 7.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a digital synchronous “latched” output (CP0), or a
digital asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
7.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+) and negative
(CP0-) input. The analog input multiplexers are completely under software control and configured using
SFR registers. See Section “7.6. Comparator0 Analog Multiplexer” on page 98 for details on how to select
and configure Comparator inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be
configured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how
to configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level
of digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
VDD
CPT0MD
CP0
Interrupt
P1.0
P1.1
CP0 +
CP0 -
CP0
Rising-edge
CP0
Falling-edge
+
D ^SET Q
D ^SET Q
-
Q CLR
Q CLR
GND
(SYNCHRONIZER)
(ASYNCHRONOUS)
Reset
Decision
Tree
Interrupt
Logic
CP0
Crossbar
CP0A
Figure 7.1. Comparator 0 Functional Block Diagram
Rev. 1.1
93