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C8051F980-C-GM Datasheet, PDF (145/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU
C8051F99x-C8051F98x
SFR Definition 13.4. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
Name PT3
PCP0 PPCA0 PADC0 PWADC0 PRTC0A
Type R/W
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
SFR Page = All; SFR Address = 0xF6
Bit Name
Function
7
PT3 Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
6 Unused Read = 0b. Write = Don’t care.
5 PCP0 Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
4 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
3 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
2 PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
1 PRTC0A SmaRTClock Alarm Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
0
PSMB0
R/W
0
Rev. 1.2
145