C8051F980-C-GM Datasheet, PDF (32/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
3. Pinout and Package Definitions
Name
V_DD
Table 3.1. Pin Definitions for the C8051F99x-C8051F98x
Pin Numbers
‘F980/1/2
‘F983/5
‘F990/1
-GM
‘F986/7 ‘F986/7
‘F988/9 ‘F988/9
‘F996/7 ‘F996/7
-GM -GU
Type
Description
4
3
6
P In Power Supply Voltage. Must be 1.8 to 3.6 V.
GND
3, 12
2
5
G Required Ground.
RST/
5
6
9
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset
by driving this pin low for at least 15 µs. A 1 k to 5 k
pullup to V_DD is recommended. See Section “18. Reset
Sources” on page 181 Section for a complete
description.
C2CK
D I/O _{Clock signal for the C2 Debug Interface.}
P2.7/
6
7
10 D I/O Port 2.7. This pin can only be used as GPIO. The
Crossbar cannot route signals to this pin and it cannot be
configured as an analog input. See Port I/O Section for a
complete description.
C2D
D I/O Bi-directional data signal for the C2 Debug Interface.
P1.6/
8
9
12 D I/O Port 1.6. See Port I/O Section for a complete description.
XTAL3
P1.7/
7
A In SmaRTClock Oscillator Crystal Input.
See Section 20 for a complete description.
8
11 D I/O Port 1.7. See Port I/O Section for a complete description.
XTAL4
A Out SmaRTClock Oscillator Crystal Output.
See Section 20 for a complete description.
P0.0/
2
24
3 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
V_REF*
A In _{External VREF Input.}
See Section “5.9. Voltage and Ground Reference
Options” on page 88.
*Note: Available only on the C8051F980/2/6/8 and C8051F990/6 devices.
32
Rev. 1.2