C8051F980-C-GM Datasheet, PDF (27/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
1.3. Serial Ports
The C8051F99x-C8051F98x Family includes an SMBus/I²C interface, a full-duplex UART with enhanced
baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in
hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.4. Programmable Counter Array
An on-chip programmable counter/timer array (PCA) is included in addition to the four 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three
programmable capture/compare modules. The PCA clock is derived from one of seven sources: the
system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input
(ECI), the system clock, the external oscillator clock source divided by 8, or the SmaRTClock divided by 8.
Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture,
software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output.
Additionally, Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system
reset, Module 2 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and
External Clock Input may be routed to Port I/O via the Digital Crossbar.
SYSCLK /12
SY S C LK /4
T im e r 0 O ve rflo w
ECI
SYSCLK
E xtern al C lo ck /8
S m aR T C lock/8
PCA
CLOCK
MUX
1 6 -B it C o u n te r/ T im e r
C a p tu re /C o m p a re
M o d u le0
C a p tu re /C o m p a re
M o d u le1
C apture / C om pare
M o du le 2 / W D T
C rossbar
P ort I/O
Figure 1.15. PCA Block Diagram
Rev. 1.2
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