C8051F980-C-GM Datasheet, PDF (198/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
20.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in Table 20.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
Table 20.1. SmaRTClock Internal Registers
SmaRTClock SmaRTClock
Address
Register
Register Name
0x00–0x03 CAPTUREn SmaRTClock Capture
Registers
0x04
RTC0CN SmaRTClock Control
Register
0x05
RTC0XCN SmaRTClock Oscillator
Control Register
0x06
RTC0XCF SmaRTClock Oscillator
Configuration Register
0x08–0x0B
ALARMn SmaRTClock Alarm
Registers
Description
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
Controls the operation of the SmaRTClock State
Machine.
Controls the operation of the SmaRTClock
Oscillator.
Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
20.1.1. SmaRTClock Lock and Key Functions
The SmaRTClock Interface has an RTC0KEY register for legacy reasons, however, all writes to this regis-
ter are ignored. The SmaRTClock interface is always unlocked on C8051F99x-C8051F98x.
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Rev. 1.2