C8051F980-C-GM Datasheet, PDF (158/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
14.6. Minimizing Flash Read Current
The Flash memory in the C8051F99x-C8051F98x devices is responsible for a substantial portion of the
total digital supply current when the device is executing code. Below are suggestions to minimize Flash
read current.
1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the interrupt flag.
Idle Mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no
more than three system clock cycles. See the Power Management chapter for details on the various
low-power operating modes.
2. C8051F99x-C8051F98x devices have a one-shot timer that saves power when operating at system
clock frequencies of 14 MHz or less. The one-shot timer generates a minimum-duration enable signal
for the Flash sense amps on each clock cycle in which the Flash memory is accessed. This allows the
Flash to remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 14 MHz, the system clock cycle becomes short enough that the one-shot
timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces
power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting
the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot, clear the BYPASS bit to logic 0.
3. Flash read current depends on the number of address lines that toggle between sequential Flash read
operations. In most cases, the difference in power is relatively small (on the order of 5%). 

The Flash memory is organized in rows of 64 bytes. A substantial current increase can be detected
when the read address jumps from one row in the Flash memory to another. Consider a 3-cycle loop
(e.g., SJMP $, or while(1);) which straddles a Flash row boundary. The Flash address jumps from one
row to another on two of every three clock cycles. This can result in a current increase of up 30% when
compared to the same 3-cycle loop contained entirely within a single row. 

To minimize the power consumption of small loops, it is best to locate them within a single row, if
possible. To check if a loop is contained within a Flash row, divide the starting address of the first
instruction in the loop by 64. If the remainder (result of modulo operation) plus the length of the loop is
less than 63, then the loop fits inside a single Flash row. Otherwise, the loop will be straddling two
adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to
another will occur on relatively few clock cycles, and any resulting increase in operating current will be
negligible.
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