C8051F980-C-GM Datasheet, PDF (146/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
SFR Definition 13.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
Name
ECSEOS ECSDC ECSCPT
ERTC0F EMAT
Type ^R/W
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
SFR Page = All;SFR Address = 0xE7
Bit Name
Function
7 Unused Read = 0b. Write = Don’t care.
6 ECSEOS Enable Capacitive Sense End of Scan Interrupt.
0: Disable Capacitive Sense End of Scan interrupt.
1: Enable interrupt requests generated by CS0EOS.
5 ECSDC Enable Capacitive Sense Digital Comparator Interrupt.
0: Disable Capacitive Sense Digital Comparator interrupt.
1: Enable interrupt requests generated by CS0CMPF.
4 ECSCPT Enable Capacitive Sense Conversion Complete Interrupt.
0: Disable Capacitive Sense Conversion Complete interrupt.
1: Enable interrupt requests generated by CS0INT.
3 Unused Read = 0b. Write = Don’t care.
2 ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
1
EMAT Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0 EWARN Enable Supply Monitor Early Warning Interrupt.
This bit sets the masking of the Supply Monitor Early Warning interrupt.
0: Disable the Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by the Supply Monitor.
0
EWARN
R/W
0
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Rev. 1.2