C8051F980-C-GM Datasheet, PDF (323/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
DOCUMENT CHANGE LIST
Revision 0.3 to Revision 0.4
 QFN-20 package and landing diagram updated.
Revision 0.4 to Revision 1.0
 IREF0CF register description updated.
 Updated ADC0 Chapter Text.
 Corrected an error in the Product Selector Guide.
 Updated SmaRTClock chapter to indicate how the Alarm value should be set when using Auto Reset
and the LFO.
 Updated electrical specifications to fill TBDs and updated power specifications based on Rev B
characterization data.
 Added a note to the OSCICL register description.
 Added a note to the CRC0CN register description.
 Updated equation in the CRC0CNT register description.
 Updated Power On Reset description.
Revision 1.0 to Revision 1.1
 Removed references to AN338.
Revision 1.1 to Revision 1.2
 Removed QuickSense references.
 Updated part numbers to Revision C in “Ordering Information” on page 31 and added Figure 3.4,
Figure 3.5, and Figure 3.6 to identify the silicon revision.
 Updated REVID register (SFR Definition 14.2) and REVID C2 register (C2 Register Definition 27.3) with
the 0x02 value for Revision C.
 Updated Figure “7.3 CP0 Multiplexer Block Diagram” on page 98 to remove the bar over the CPnOUT
signals.
 Updated the “Reset Sources” on page 181 chapter to reflect the correct state of the RST pin during
power-on reset.
 Updated Figure “1.14 Port I/O Functional Block Diagram” on page 26 and Figure “21.1 Port I/O
Functional Block Diagram” on page 215 to mention P1.4 is not available on 20-pin devices.
 Removed references to the EMI0CN register, which does not exist.
 Updated Figure “8.2 Auto-Scan Example” on page 103 to refer to the correct pins.
 Updated POR Monitor Threshold (V_POR) Brownout Condition (VDD Falling) specification minimum,
typical, and maximum values.
 Updated the reset value of the CLKSEL register (SFR Definition 19.1).
 Updated description of WEAKPUD in SFR Definition 21.3.
 Corrected SFR addresses for P0DRV (SFR Definition 21.12), P1DRV (SFR Definition 21.17), P2DRV
(SFR Definition 21.20), PMU0MD (SFR Definition 15.3), FLSCL (SFR Definition 14.5), REF0CN (SFR
Definition 5.15), CS0SCAN0 (SFR Definition 8.5), and CS0SCAN1 (SFR Definition 8.6).
 Replaced all instances of V_BAT with V_DD.
 Added a note to “11.1. Accessing XRAM” , “15.5. Sleep Mode” , and “18. Reset Sources” regarding an
issue with the first address of XRAM.
 Added a note to “15.5. Sleep Mode” and “19. Clocking Sources” regarding using the internal low power
Rev. 1.2
323