C8051F980-C-GM Datasheet, PDF (253/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values Read
Current SMbus State
Typical Response Options
Values to
Write
1110
0
0
X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
0 0 X 1100
A master data or address byte Set STA to restart transfer.
0 0 0 was transmitted; NACK
received.
Abort transfer.
1 0 X 1110
01X —
Load next data byte into SMB0-
DAT.
0 0 X 1100
End transfer with STOP.
01X —
1100
0
0
A master data or address byte End transfer with STOP and start
1 was transmitted; ACK
another transfer.
1
1
X
—
received.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data 0 0 X 1000
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte,
and send STOP.
0
1
0
—
Send NACK to indicate last byte,
and send STOP followed by
1 1 0 1110
START.
1000
1
0
X
A master data byte was
received; ACK requested.
Send ACK followed by repeated
START.
1
0
1
1110
Send NACK to indicate last byte,
and send repeated START.
1
0
0
1110
Send ACK and switch to Master
Transmitter Mode (write to
0 0 1 1100
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to 0 0 0 1100
SMB0DAT before clearing SI).
Rev. 1.2
253