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C8051F980-C-GM Datasheet, PDF (57/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU | |||
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C8051F99x-C8051F98x
Table 4.4. Reset Electrical Characteristics
VDD = 1.8 to 3.6 V, â40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
VDD Monitor Threshold
(VRST)
IOL = 1.4 mA,
VDD = 12.0 to 3.6 V
VDD = 10.9 to 2.0 V
VDD = 12.0 to 3.6 V
VDD = 10.9 to 2.0 V
RST = 10.0 V, VDD = 1.8 V
RST = 10.0 V, VDD = 13.6 V
Early Warning
Reset Trigger
(all power modes except Sleep)
â
â
0.6
V
VDD â 0.6 â
â
V
0.7 x VDD â
â
V
â
â
0.6
V
â
â 0.3 x VDD V
â
4
â
µA
â
20
30
1.8 1.85 1.9
V
1.7 1.75 1.8
VDD Ramp Time for Power
On
VDD Ramp from 0â1.8 V
â
â
3
ms
POR Monitor Threshold
Brownout Condition (VDD Falling)
0.75 1.0 1.3
(VPOR)
V
Recovery from Brownout (VDD Rising)
â 1.75 â
Missing Clock Detectorï
Timeout
Time from last system clock rising edge
to reset initiation
100
650 1000
µs
Minimum System Clock w/ System clock frequency which triggers
Missing Clock Detector
a missing clock detector timeout
â
7
10
kHz
Enabled
Reset Time Delay
Delay between release of any reset
source and code
execution at location 0x0000
â
10
â
µs
Minimum RST Low Time to
Generate a System Reset
15
â
â
µs
VDD Monitor Turn-on Time
VDD Monitor Supply ï
Current
â
300
â
ns
â
7
â
µA
Rev. 1.2
57
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