C8051F980-C-GM Datasheet, PDF (129/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
10.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F99x-C8051F98x devices implement
8 kB (C8051F980/1/6/7, C8051F990/1/6/7), 4 kB (C8051F982/3/8/9), or 2 kB (C8051F985) of this program
memory space as in-system, re-programmable Flash memory, organized in a contiguous block from
addresses 0x0000 to 0x1FFF (8 kB devices), 0x0FFF (4 kB devices), or 0x07FF (2 kB devices). The last
byte of this contiguous block of addresses serves as the security lock byte for the device. Any addresses
above the lock byte are reserved.
C8051F980/1/6/7
C8051F990/1/6/7
Unpopulated
Address Space
(Reserved)
Lock Byte
Lock Byte Page
Flash Memory Space
C8051F982/3/8/9
C8051F985
0xFFFF
0xFFFF
0x2000
0x1FFF
0x1FFE
0x1E00
0x1BFF
Unpopulated
Address Space
(Reserved)
Unpopulated
Address Space
(Reserved)
Lock Byte
Lock Byte Page
0x1000
0x0FFF
0x0FFE
0x0E00
0x0BFF
Lock Byte
Lock Byte Page
0x0000
Flash Memory Space
0x0000
Flash Memory Space
Figure 10.2. Flash Program Memory Map
0xFFFF
0x0800
0x07FF
0x07FE
0x0600
0x05FF
0x0000
10.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F99x-C8051F98x devices, the MOVX instruction is normally used to read and write on-chip XRAM,
but can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always
used to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash
access feature provides a mechanism for the C8051F99x-C8051F98x to update program code and use
the program memory space for non-volatile data storage. Refer to Section “14. Flash Memory” on
page 150 for further details.
10.2. Data Memory
The C8051F99x-C8051F98x device family include 512 bytes of RAM data memory. 256 bytes of this
memory is mapped into the internal RAM space of the 8051. The remainder of this memory is on-chip
“external” memory. The data memory map is shown in Figure 10.1 for reference.
10.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
Rev. 1.2
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