C8051F980-C-GM Datasheet, PDF (215/325 Pages) Silicon Laboratories – Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU

C8051F99x-C8051F98x
21. Port Input/Output
Digital and analog resources are available through 16 or 17 I/O pins. Port pins are organized as three byte-
wide ports. Port pins P0.0–P1.7 can be defined as digital or analog I/O. Digital I/O pins can be assigned to
one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by
the internal analog resources. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal
(C2D). See Section “27. C2 Interface” on page 319 for more details.
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section 21.3 for more information on the Crossbar.
All Port I/Os can tolerate voltages up to the supply rail when used as digital inputs or open-drain outputs.
For Port I/Os configured as push-pull outputs, current is sourced from the V_DD supply. Port I/Os used for
analog functions can operate up to the V_DD supply voltage. See Section 21.1 for more information on Port
I/O operating modes and the electrical specifications chapter for detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
2
UART
4
SPI0
2
SMBus
CP0
4
Output
SYSCLK
PCA
4
2
T0, T1
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
1
P2
(P2.7)
Priority
Decoder
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
Digital
Crossbar
8
8
1
P0
I/O
Cells
P1
I/O
Cells
P2
I/O
Cell
P0.0
P0.7
P1.0
P1.7*
*P1.4 is not available on
20-pin devices.
P2.7
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
Figure 21.1. Port I/O Functional Block Diagram
Rev. 1.2
215